1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-04-19 David J. Corbett CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT QUADRUPLE BU
3、S BUFFER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-21 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04705 REV A PAGE 1 OF 10 AMSC N/A 5962-V039-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN
4、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT quadruple bus buffer with 3-state outputs microcircuit, with an operating temperature range of -40C to +125C. 1.
5、2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04705 - 01 X E Drawing Device type Case outline Lead finish nu
6、mber (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVT125-EP 3.3-V ABT quadruple bus buffer with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MO-153
7、Plastic small-outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduc
8、tion or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range
9、applied to any output in the high state or power-off state (VO) . -0.5 V to 7 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal imped
10、ance (JA) . 113C/W 4/ Storage temperature range (TSTG) . -65C to 150C 5/ 1.4 Recommended operating conditions. 6/ 7/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Maximum high
11、level output current (IOH) . -32 mA Maximum low level output current (IOL) . 32 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Operating free-air temperature range (TA) -40C to +125C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent d
12、amage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
13、 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Long-term high-te
14、mperature storage and/or extended use at maximum recommended operating conditions may result in a reduction in overall device life. 6/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 7/ Use of this product beyond the manufacturers design rules or stated p
15、arameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO
16、 SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 4 2. APPLICABLE DOCUMENTS ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies
17、of these documents are available online at http:/www.eia.org or from the Electronic Industries Alliance, Technology Strategy & Standards Department, 2500 Wilson Boulevard, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part num
18、ber as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteri
19、stics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case o
20、utline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test cir
21、cuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 5
22、TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 125C All -1.2 V High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3.0 V 2
23、 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 Input current IIVI= 5.5 V 0 V or 3.6 V 10 A Control inputs. VI= VCCor GND 3.6 V 1 Data inputs. VI= VCC1 Data inputs. VI= 0 V -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 10
24、0 A Input current (hold) II(hold)Data inputs. VI= 0.8 V 3 V 75 AData inputs. VI= 2 V -75 3-state output current high IOZHVO= 3 V 3.6 V 5 A 3-state output current low IOZLVO= 0.5 V 3.6 V -5 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without l
25、icense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Quiescent supply current ICCOutputs high
26、 VI= VCCor GND IO= 0 A 3.6 V 25C, -40C to 125C All 0.19 mA Outputs low. VI= VCCor GND IO= 0 A 7 Outputs disabled. VI= VCCor GND IO= 0 A 0.19 Quiescent supply current delta ICC2/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP
27、pF Output capacitance CoVO= 3 V or 0 V 8 TYP pF Propagation delay time, A to Y tPLHCL= 50 pF See figure 5. 2.7 V 25C, -40C to 125C 4.7 ns 3.3 V 0.3 V 1 4.2 tPHL2.7 V 5.13.3 V 0.3 V 1 4.1 Propagation delay time, output enable, OE to Y tPZH2.7 V 6.2 ns 3.3 V 0.3 V 1 4.9 tPZL2.7 V 6.73.3 V 0.3 V 1.1 4.
28、9 Propagation delay time, output disable, OE to Y tPHZ2.7 V 5.9 ns 3.3 V 0.3 V 1.8 5.3 tPLZ2.7 V 4.23.3 V 0.3 V 1.3 4.7 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessar
29、ily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This is the increase in supply current for each input that is at the specified TTL vol
30、tage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeter
31、s Inches Min Max Min Max Min Max Min Max A - 1.20 - .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 BSC .026 BSC c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 4.90 5.10 .193 .201 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This
32、case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
33、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 8 (each buffer) Inputs Output OE A Y L L H H L X H L Z H = High voltage level Z = High-impedance state L = Low voltage level X = Immaterial FIGURE 2. Truth table. FIGURE 3. Logic diagram. Devi
34、ce type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1OE 8 3Y 2 1A 9 3A 3 1Y 10 3OE 4 2OE 11 4Y 5 2A 12 4A 6 2Y 13 4OE 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
35、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for
36、an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one at a time with one input tra
37、nsition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04705 REV A PAGE 10 4. VERIFICATION 4.1 Produ
38、ct assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitiv
39、e devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensit
40、ive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are
41、provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Ve
42、ndor part number Top side marking V62/04705-01XE 01295 SN74LVT125QPWREP LVT125E 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
