1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish for device 03. Update boilerplate. - CFS 05-12-02 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 13-09-12 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME C
2、OLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B B B B B B B B B B B PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES RE
3、V B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FLOATING POINT DIGITAL SIGNAL PROCESSOR, MONO
4、LITHIC SILICON YY MM DD 05-01-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04754 REV B PAGE 1 OF 52 AMSC N/A 5962-V082-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A
5、CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Floating-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Num
6、ber. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04754 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 D
7、evice type(s). 1/ Device type Generic Circuit function 01 SM320C6712-EP Floating Point Digital Signal Processor 02 SM320C6712C-EP Floating Point Digital Signal Processor 03 SM320C6712D-EP Floating Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outlin
8、e letter Number of pins JEDEC PUB 95 Package style X 256 JEDEC MO-151 Plastic ball grid array Y 272 JEDEC MO-151 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solde
9、r dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEF
10、ENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage ranges, (CVDD): 3/ Device type 02 and 03 only -0.3 V to +1.8 V Device type 01 . -0.3 V to +2.3 V Supply voltage ranges, (DVDD) . -0.3 V to +4.0 V 3/
11、Input voltage ranges: (VI): Device type 02 and 03 only -0.3 V to DVDD+ 0.5 V Device type 01 -0.3 V to +4.0 V Output voltage ranges: (VO) Device type 02 and 03 only -0.3 V to DVDD+ 0.5 V Device type 01 -0.3 V to +4.0 V Operating case temperature ranges, (TC) -40C to +105C Storage temperature range, (
12、TSTG) -65C to +150C 1.4 Recommended operating conditions. Min Max Unit Supply voltage, Core (CVDD) 4/ Device type 02 and 03 only 1.14 5/ 1.32 V Device type 01 1.71 1.89 Supply voltage, I/O (DVDD) 4/ Device type 02 and 03 only 3.13 3.47 V Device type 01 3.14 3.46 Supply ground, (VSS) 0 0 V High level
13、 input voltage, (VIH) Device type 02 and 03 only All signals except CLKS1, DR1, RESET 2 V CLKS1, DR1, RESET 2 Device type 01 and 02 2 Low level input voltage, (VIL) Device type 02 and 03 only All signals except CLKS1, DR1, RESET 0.8 V CLKS1, DR1, RESET 0.3*DVDDDevice type 01 0.8 2/ Stresses beyond t
14、hose listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-ra
15、ted conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. 4/ For device type 01, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O supply. For device type 02 and 03, the core supply should b
16、e powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. 5/ These values are compatible with existing 1.26 V designs. Provided by IH
17、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 4 1.4 Recommended operating conditions - Continued. Min Max Unit High level output current, (IOH) Device type 01
18、 All signals except CLKOUT1, CLKOUT2, and ECLKOUT -4 mA CLKOUT1, CLKOUT2, and ECLKOUT -8 Device type 02 6/ All signals except ECKLOUT, CLKOUT2, CLKOUT3, CLKS1, and DR1 -8 mA ECKLOUT, CLKOUT2, CLKOUT3 -16 Device type 03 5/ All signals except ECKLOUT, CLKOUT2, CLKS1, and DR1 -8 mA ECKLOUT and CLKOUT2
19、-16 Low level output current, (IOL) Device type 01 All signals except CLKOUT1, CLKOUT2, and ECLKOUT 4 mA CLKOUT1, CLKOUT2, and ECLKOUT 8 Device type 02 5/ All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1, and DR1 8 mA ECKLOUT, CLKOUT2, CLKOUT3 16 CLKS1 and DR1 3 Device type 03 5/ All signals exce
20、pt ECKLOUT, CLKOUT2, CLKS1, and DR1 8 mA ECKLOUT and CLKOUT2 16 CLKS1 and DR1 3 Operating case temperature, (TC) -40 105 C Thermal resistance characteristics for case X (device type 01 only) Air Flow (m/s) 7/ C/W Junction to case, (RJC) N/A 6.4 Junction to free air, (RJA) 0.0 25.5 Junction to free a
21、ir, (RJA) 0.5 23.1 Junction to free air, (RJA) 1.0 22.3 Junction to free air, (RJA) 2.0 21.2 6/ Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see manufacturer data device specific IBIS models. 7/ m/s = meters per second. Provided by IHSNot for
22、ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 5 1.4 Recommended operating conditions - Continued. Thermal resistance characteristics for case Y (device type 02 and 03
23、only) Air Flow (m/s) 7/ C/W Junction to case, (RJC) N/A 9.7 Junction to package top (PsiJT) 0.0 1.5 Junction to board, (RJB) N/A 19 Junction to free air, (RJA) 0.0 22 Junction to free air, (RJA) 0.5 21 Junction to free air, (RJA) 1.0 20 Junction to free air, (RJA) 2.0 19 Junction to free air, (RJA)
24、4.0 18 Junction to board, (PsiJB) 0.0 16 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association,
25、3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (op
26、tional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, an
27、d table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall
28、be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Test load circuits. The test load circuits shall be as specified in figure 4. 3.5.5 Board level input/output timings. The board level input/output timings shall be as specified in figure 5. 3.5.6
29、 Timing waveforms. The timing waveforms shall be as shown in figure 6-40. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 6 TABLE I. Electrical pe
30、rformance characteristics. 1/ Test Symbol Test condition 2/ Device type Limits Unit Min Max High level output voltage VOHAll signals DVDD= min, IOH= max 01 2.4 V All signals except CLKS1 and DR1 02, 03 2.4 Low level output voltage VOLAll signals DVDD= min, IOL= max 01 0.4 V All signals except CLKS1
31、and DR1 02, 03 0.4 CLKS1 and DR1 02, 03 0.4 Input current IIAll signals VI= VSSto DVDD01 150 A All signals except CLKS1 and DR1 02, 03 170 CLKS1 and DR1 02, 03 10 Off state output current IOZAll signals VO= DVDD or 0 V 01 10 A All signals except CLKS1 and DR1 02, 03 170 CLKS1 and DR1 02, 03 10 Suppl
32、y current, CPU + CPU memory access 3/ IDD2VCVDD= NOM, CPU clock = 100 MHz 01 336 Typ mA Supply current, peripherals 3/ IDD2V01 180 Typ Core supply current IDD2VCVDD= 1.26 V, CPU clock = 150 MHz 02 430 Typ mA CVDD= 1.26 V, CPU clock = 167 MHz 03 475 Typ Supply current, I/O pins 3/ IDD3VDVDD= NOM, CPU
33、 clock = 100 MHz 01 50 Typ mA I/O supply current IDD3VDVDD= 3.3 V, EMIF speed = 100 MHz 02, 03 75 Typ mA Input capacitance CiAll 7 pF Output capacitance CoAll 7 pF See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUP
34、PLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 7 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test conditions 2/ Limits Limits Unit Min Max Min Max INPUT AND OUTPUT CLOCKS Timing requirements for CLKIN 4/ 5/ device type 01
35、-100 CLKMODE = x4 CLKMODE = x1 1 Cycle time, CLKIN tc(CLKIN)See figure 6 40 10 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.45C 4 Transaction time, CLKIN tt(CLKIN)5 1 Timing requirements for CLKIN 4/ 5/ 6/ device type 02 and 03 -167 PLL MODE (PLLE
36、N = 1) BYPASS MODE (PLLEN = 0) 1 Cycle time, CLKIN tc(CLKIN)See figure 6 6 83.3 6 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.4C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.4C 4 Transaction time, CLKIN tt(CLKIN)5 5 Switching characteristics for CLKOUT1 7/ 8/ 9/ device type 01 only -100 CLKMODE
37、 = x4 CLKMODE = x4 1 Cycle time, CLKOUT1 tc(CKO1)See figure 7 P-0.7 P+0.7 P-0.7 P+0.7 ns 2 Pulse duration, CLKOUT1 high tw(CKO1H)(P/2)-0.7 (P/2)+0.7 PH-0.7 PH+0.7 3 Pulse duration, CLKOUT1 low tw(CKO1L)(P/2)-0.7 (P/2)+0.7 PH-0.7 PH+0.7 4 Transition time, CLKOUT1 tt(CKO1)0.6 0.6 Switching characteris
38、tics for CLKOUT2 7/ 9/ device type 01 -100 1 Cycle time, CLKOUT2 tc(CKO2)See figure 8 2P-0.7 2P+0.7 ns 2 Pulse duration, CLKOUT2 high tw(CKO2H)P-0.7 P+0.7 3 Pulse duration, CLKOUT2 low tw(CKO2L)P-0.7 P+0.7 4 Transition time, CLKOUT2 tt(CKO2)0.6 Switching characteristics for CLKOUT2 7/ 10/ device typ
39、e 02 and 03 -167 1 Cycle time, CLKOUT2 tc(CKO2)See figure 8 C2-0.8 C2+0.8 ns 2 Pulse duration, CLKOUT2 high tw(CKO2H)(C2/2)-0.8 (C2/2)+0.8 3 Pulse duration, CLKOUT2 low tw(CKO2L)(C2/2)-0.8 (C2/2)+0.8 4 Transition time, CLKOUT2 tt(CKO2)2 See notes at end of table. Provided by IHSNot for ResaleNo repr
40、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 8 TABLE I. Electrical performance characteristics Continued. No Test Symbol Test conditions 2/ Limits Limits Unit Min Max Min Max INPU
41、T AND OUTPUT CLOCKS (Continued) Switching characteristics for CLKOUT3 7/ 11/ device type 02 and 03 Device type 02-167 Device type 03-167 1 Cycle time, CLKOUT3 tc(CKO3)See figure 9 C3-0.6 C3+0.6 C3-0.9 C3+0.9 ns 2 Pulse duration, CLKOUT3 high tw(CKO3H)(C3/2)-0.6 (C3/2)+0.6 (C3/2)-0.9 (C3/2)+0.9 3 Pul
42、se duration, CLKOUT3 low tw(CKO3L)(C3/2)-0.6 (C3/2)+0.6 (C3/2)-0.9 (C3/2)+0.9 4 Transition time, CLKOUT3 tt(CKO3)2 3 5 Delay time, CLKIN high to CLKOUT3 valid td(CKINH-CKO3V)1.5 6.5 1.5 7.5 Timing requirements for ECLKIN 4/ -100 -167 ns 1 Cycle time, ECLKIN tc(EKI)See figure 10 15 10 2 Pulse duratio
43、n, ECLKIN high tw(ECKIH)6.8 4.5 3 Pulse duration, ECLKIN low tw(ECKIL)6.8 4.5 4 Transaction time, ECLKIN tt(EKI)3 3 Switching characteristics for ECLKOUT 7/ 12/ 13/ -100 -167 1 Cycle time, CLKOUT tc(EKO)See figure 11 E-0.7 E+0.7 E-0.9 E+0.9 ns 2 Pulse duration, ECLKOUT high tw(ECKOH)EH-0.7 EH+0.7 EH
44、-09 EH+0.9 3 Pulse duration, ECLKOUT low tw(ECKOL)EL-0.7 EL+0.7 EL-09 EL+0.9 4 Transition time, ECLKOUT tt(EKO)0.6 2 5 Delay time, ECLKIN high to ECLKOUT high td(EKIH-EKOH)1 7 1 6.5 6 Delay time, ECLKIN low to ECLKOUT low td(EKIL-EKOL)1 7 1 6.5 See notes at end of table. Provided by IHSNot for Resal
45、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04754 REV B PAGE 9 TABLE I. Electrical performance characteristics Continued. No Test Symbol Test conditions 2/ Limits Limits Unit Min Max Min
46、Max ASYNCHRONOUS MEMORY TIMING Timing requirements for asynchronous memory cycles 14/ 15/ -100 -167 3 Setup time, EDx valid before ARE high tsu(EDV-AREH)See figure 12 13 6.5 ns 4 Hold time, EDx valid after ARE high th(AREH-EDV)1 1 6 Setup time, ARDY valid before ECLKOUT high tsu(ARDY-EKOH)6 3 7 Hold
47、 time, ARDY valid after ECLKOUT high th(EKOH-ARDY)1.7 2.3 Switching characteristics for asynchronous memory cycles 15/ 16/ 17/ -100 -167 1 Output setup time, select signals valid to ARE low tosu(SELV-AREL)See figure 12 RS*E-3 RS*E-1.7 ns 2 Output hold time, ARE high to select signals invalid toh(ARE
48、H-SELIV)RH*E-3 RH*E-1.7 5 Delay time, ECKLOUT high to ARE valid td(EKOH-AREV)1.5 11 1.5 7 8 Output setup time, select signals valid to AWE low tosu(SELV-AWEL)WS*E-3 WS*E-1.7 9 Output hold time, AWE high to select signals and EDx invalid toh(AWEH-SELIV)WH*E-3 WH*E-1.7 10 Delay time, ECLKOUT high to AWE valid td(EKOH-AWEV)1.5 11 1.5 7 11 Output setup time, ED valid to A
