1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add case outline “Z”. - CFS 05-08-26 Thomas M. Hess B Update boilerplate paragraphs to current MIL-PRF-3853 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-
2、3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B B B B B B B B B B B B B B B B B PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS O
3、F PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL SIGNAL PROCESSORS, MONOLITHIC SILICO
4、N YY MM DD 05-03-23 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05601 REV B PAGE 1 OF 58 AMSC N/A 5962-V005-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO
5、. 16236 DWG NO. V62/05601 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance floating-point digital signal processor microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manu
6、facturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05601 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s)
7、. 1/ Device type Generic Circuit function 01 SM320F2810-EP Digital Signal Processors 02 SM320F2811-EP Digital Signal Processors 03 SM320F2812-EP Digital Signal Processors 04 SM320C2810-EP Digital Signal Processors 05 SM320C2811-EP Digital Signal Processors 06 SM320C2812-EP Digital Signal Processors
8、1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 179 Plastic ball grid array Z 176 JEDEC MS-026 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the de
9、vice manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Provided by IHSNot for ResaleNo reproduction
10、 or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05601 REV B PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage ranges, (VDDIO, VDDA1, VDDA2, VDDAIO, AVDDREFBG) . -0.3 V to +4.6 V Supply voltage ranges, (
11、VSSA1/VSSA2to VDDA1/ VDDA2/ AVDDREFBG) -0.3 V to +4.6 V VSS1to VDD1-0.3 V to +2.5 V Supply voltage ranges, (VDD, VDD1) -0.5 V to +2.5 V VDD3VFL range . -0.3 V to +4.6 V Input voltage range, (VIN) . -0.3 V to +4.6 V Output voltage range, (VO) . -0.3 V to +4.6 V Input clamp current, IIK(VINVDDIO) . 20
12、 mA 3/ Output clamp current, IOK(VOVDDIO) 20 mA Analog input (ADCIN) clamp current, total (max) . 20 mA 4/ Operating ambient temperature ranges, (TA : M version (GHH) . -55C to +125C Storage temperature range, (TSTG) -65C to +150C 5/ 1.4 Recommended operating conditions. Device supply voltage, I/O,
13、(VDDIO) . +3.14 V to +3.47 V Device supply voltage, CPU (VDD, VDD1): 1.8 V (135 MHz) . +1.71 V to 1.89 V 1.9 V (150 MHz) . +1.81 to +2.0 V Supply ground, (VSS) 0 V ADC supply voltage (VDDA!, VDDA2, AVDDREFBG, VDDAIO) . +3.14 V to +3.47 V Flash programming supply voltage, (VDD3VFL) . +3.14 V to +3.47
14、 V Device clock frequency (system clock), (fSYSCLKOUT) : VDD= 1.9 V 5% 2 MHz to 150 MHz VDD= 1.8 V 5% 2 MHz to 135 MHz High level input voltage, (VIH) : All inputs except XCLKIN . +2.0 V to VDDIOXCLKIN ( 50 A max) . +0.7VDDto VDDMaximum low level input voltage, (VIL) : All inputs except XCLKIN . +0.
15、8 V XCLKIN ( 50 A max) . +0.3VDDMaximum high level output source current, VOH= 2.4 V (IOH) : All I/Os except group 2 . -4 mA Group 2 6/ . -8 mA Maximum low level output sink current, VOL= VOLmax (IOL) : All I/Os except group 2 . 4 mA Group 2 6/ . 8 mA Ambient temperature, (M version, ) (See figure 4
16、 and figure 5) -55C to +125C 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions
17、” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ Continuous clamp current per pin is 2 mA. 4/ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDAor below VSS.The continuous clamp
18、current per pin is 2 mA. 5/ Long term high temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. 6/ Group 2 pins are as follows: XINTF pins, PDPINTA , TDO, XCLOUT, XF, ENU0, and EMU1. Provided by IHSNot for ResaleNo reproduction o
19、r networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05601 REV B PAGE 4 1.5 Recommended operating conditions - Continued. Thermal resistance characteristics: Parameter Case X Uniit PsJT0.658 C/W JA42.57 C/W JC16.08
20、 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S,
21、Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit
22、 container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, constr
23、uction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block dia
24、gram. The block diagram shall be as specified in figure 3. 3.5.4 FIT rate versus operating junction temperature. The FIT rate versus operating junction temperature shall be as specified in figure 4. 3.5.5 Package life time versus operating junction temperature. The package life time versus operating
25、 junction temperature shall be as specified in figure 5. 3.5.6 Current consumption graphs. The current consumption graphs shall be as specified in figure 6. 3.5.7 Test load circuits. The test load circuits shall be as specified in figure 7. 3.5.8 Timing waveforms. The timing waveforms shall be as sh
26、own in figure 8- 42. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05601 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ No Test Symbol Test con
27、dition 2/ Limits Unit Min Max High level output voltage VOHIOH= IOH max2.4 V IOH= 50 A VDDIO 0.2 Low level output voltage VOLIOL = IOL max0.4 V Low level input current With pull up IILVDDIO= 3.3 V, VIN= 0 V All I/Os 3/ (including XRS ) except EVB -80 -190 A GPIOB/EVB -13 -35 With pull down VDDIO= 3.
28、3 V, VIN= 0 V 2 High level input current With pull up IIHVDDIO= 3.3 V, VIN= VDD2 A With pull down 28 80 Off state output current, high impedance state (off state) IOZVO= VDDIOor 0 V 2 A Input capacitance Ci2 Typ pF Output capacitance CO3 Typ pF Input clock frequency Input clock frequency fxResonator
29、 20 35 MHz Crystal 20 35 XCLKIN 4 150 Limp mode clock frequency fl2 Typ MHz XCLKIN timing requirements PLL bypassed or Enabled C8 Cycle time, XCLKIN tc(CI)See figure 8 6.67 250 ns C9 Fall time, XCLKIN tf(CI)Up to 30 MHz 6 30 MHz to 150 MHz 2 C10 Rise time, XCLKIN tr(CI)Up to 30 MHz 6 30 MHz to 150 M
30、Hz 2 C11 Pulse duration, X1/XCLKIN low as a percentage of tc(CI)tw(CIL)40 60 % C12 Pulse duration, X1/XCLKIN high as a percentage of tc(CI)tw(CIH)40 60 XCLKIN timing requirements PLL disabled C8 Cycle time, XCLKIN tc(CI)See figure 8 6.67 250 ns C9 Fall time, XCLKIN tf(CI)Up to 30 MHz 6 30 MHz to 150
31、 MHz 2 C10 Rise time, XCLKIN tr(CI)Up to 30 MHz 6 30 MHz to 150 MHz 2 C11 Pulse duration, X1/XCLKIN low as a percentage of tc(CI)tw(CIL)XCLKIN 120 MHz 40 60 % 120 3 1 Cycle time, SPICLK tc(SPC)MSee figure 23 4tc(LCO)128tc(LCO)5tc(LCO)127tc(LCO)ns 2 22/ Pulse duration, SPICLK high (clock polarity = 0
32、) tw(SPCH)M23/ 24/ 26/ 27/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)M23/ 24/ 26/ 27/ 3 22/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)M23/ 24/ 28/ 29/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)M23/ 24/ 28/ 29/ 4 22/ Delay time, SPICLK high to SPISIMO valid
33、(clock polarity = 0) td(SPCH-SIMO)M-10 -10 -10 -10 Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) td(SPCL-SIMO)M-10 -10 -10 -10 5 22/ Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) tv(SPCL-SIMO)M23/ 28/ Valid time, SPISIMO data valid after SPICLK high (clock polar
34、ity = 1) tv(SPCH-SIMO)M23/ 28/ 8 22/ Setup time, SPIOMI before SPICLK low (clock polarity = 0) tsu(SOMI-SPCL)M0 0 Setup time, SPIOMI before SPICLK high (clock polarity = 1) tsu(SOMI-SPCH)M0 0 9 22/ Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) tv(SPCL-SOMI)M25/ 26/ Valid time,
35、 SPISIMO data valid after SPICLK high (clock polarity = 1) tv(SPCH-SOMI)M25/ 26/ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05601 R
36、EV B PAGE 11 TABLE I. Electrical performance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Limits Unit Min Max Min Max SPI MASTER MODE TIMING - Continued SPI master mode external timing (clock phase = 1) 20/ 21/ SPI when (SPIBRR+1) is even or SPIBRR = 0 or 2 SPI when (SPIBRR+1) is
37、 odd and SPIBRR 3 1 Cycle time, SPICLK tc(SPC)MSee figure 24 4tc(LCO)128tc(LCO)5tc(LCO)127tc(LCO)ns 2 22/ Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)M23/ 24/ 26/ 27/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)M23/ 24/ 26/ 27/ 3 22/ Pulse duration, SPICLK low (clock polarit
38、y = 0) tw(SPCL)M23/ 24/ 28/ 29/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)M23/ 24/ 28/ 29/ 6 22/ Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) tsu(SIMO-SPCH)M23/ 23/ Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) tsu(SIMO-SPCL)M23/ 23/ 7
39、 22/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) tv(SPCH-SIMO)M23/ 23/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) tv(SPCL-SIMO)M23/ 23/ 10 22/ Setup time, SPISOMI before SPICLK high (clock polarity = 0) tsu(SOMI-SPCH)M0 0 Setup time, SPIOMI before
40、 SPICLK low (clock polarity = 1) tsu(SOMI-SPCL)M0 0 11 22/ Valid time, SPISOMI data valid after SPICLK high(clock polarity = 0) tv(SPCH-SOMI)M25/ 23/ Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) tv(SPCL-SOMI)M25/ 23/ See notes at end of table. Provided by IHSNot for ResaleNo
41、reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05601 REV B PAGE 12 TABLE I. Electrical performance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Limits Unit Min Max SPI SLAVE
42、MODE TIMING SPI slave mode external timing (clock phase = 0) 20/ 21/ 12 Cycle time, SPICLK tc(SPC)SSee figure 25 5tc(LCO) 21/ ns 13 22/ Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)S30/ 31/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)S30/ 31/ 14 22/ Pulse duration, SPICLK low
43、 (clock polarity = 0) tw(SPCL)S30/ 31/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)S30/ 31/ 15 22/ Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) td(SPCH-SOMI)S32/ Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) td(SPCL-SOMI)S32/ 16 22/ Valid time, SPISOMI da
44、ta valid after SPICLK low (clock polarity = 0) tv(SPCH-SOMI)S33/ Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) tv(SPCL-SOMI)S33/ 19 22/ Setup time, SPISIMO before SPICLK low (clock polarity = 0) tsu(SIMO-SPCL)S0 Setup time, SPISIMO before SPICLK high (clock polarity = 1) tsu(
45、SIMO-SPCH)S0 20 22/ Valid time, SPISIMO before SPICLK low (clock polarity = 0) tv(SPCL-SIMO)S31/ Valid time, SPISIMO before SPICLK high (clock polarity = 1) tv(SPCH-SIMO)S31/ SPI slave mode external timing (clock phase = 1) 20/ 21/ 12 Cycle time, SPICLK tc(SPC)SSee figure 26 8tc(LCO)ns 13 22/ Pulse
46、duration, SPICLK high (clock polarity = 0) tw(SPCH)S30/ 31/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)S30/ 31/ 14 22/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)S30/ 31/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)S30/ 31/ 17 22/ Setup time, SPISOMI before SPI
47、CLK high (clock polarity = 0) tsu(SOMI-SPCH)S34/ Setup time, SPISOMI before SPICLK low (clock polarity = 1) tsu(SOMI-SPCL)S34/ 18 22/ Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) tv(SPCH-SOMI)S33/ Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) tv(SPCL-S
48、OMI)S33/ 21 22/ Setup time, SPISIMO before SPICLK high (clock polarity = 0) tsu(SIMO-SPCH)S0 Setup time, SPISIMO before SPICLK low (clock polarity = 1) tsu(SIMO-SPCL)S0 22 22/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) tv(SPCH-SIMO)S31/ Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) tv(SPCL-SIMO)S31/ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C
