DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf

上传人:arrownail386 文档编号:689204 上传时间:2018-12-30 格式:PDF 页数:12 大小:160.45KB
下载 相关 举报
DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf_第1页
第1页 / 共12页
DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf_第2页
第2页 / 共12页
DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf_第3页
第3页 / 共12页
DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf_第4页
第4页 / 共12页
DLA DSCC-VID-V62 05608 REV B-2012 MICROCIRCUIT LINEAR WIDE BAND LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS MONOLITHIC SILICON.pdf_第5页
第5页 / 共12页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-11-29 Thomas M. Hess B Add device type 03. - phn 12-02-27 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared i

2、n accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MIC

3、ROCIRCUIT, LINEAR, WIDE BAND, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERS, MONOLITHIC SILICON YY MM DD 05-06-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05608 REV B PAGE 1 OF 12 AMSC N/A 5962-V035-12 Provided by IHSNot for ResaleNo reproduction or networking permitted wit

4、hout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance wide band, low distortion fully differential amplifiers, with an operating tem

5、perature range of -55C to +125C for device type 01 and 02 and an operating temperature range of -55C to +60C for device type 03. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control n

6、umber for identifying the item on the engineering documentation: V62/05608 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic TACircuit function 01 THS4502-EP -55C to +125C Wideband, low distortion fully diffe

7、rential amplifiers 02 THS4503-EP -55C to +125C Wideband, low distortion fully differential amplifiers 03 2/ THS4503-EP -55C to +60C Wideband, low distortion fully differential amplifiers 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Pack

8、age style X 8 JEDEC MS-012 Plastic small outline package Y 8 JEDEC M0-187 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold pla

9、te D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ The device type 02 and 03 may have low level oscillation when the die temperature (also known as the junction temperature) exceeds

10、60C. These device are not recommended for new designs where the die temperature is expected to exceeds 60C. for more information, see manufacturer data on Maximum Die temperature to Oscillation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

11、 SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 3 1.3 Absolute maximum ratings. 3/ Supply voltage, (VS) . +16.5 V Input voltage, (VI): . VS Output current, (IO) . 150 mA 4/ Differential input voltage, (VID) +4.0 V Maximum junction temperature, (TJ) +1

12、50C 5/ Maximum junction temperature, continuous operation, long term reliability, (TJ) . +125C 6/ Operating free air temperature range, (TA) (device type 01 and 02) . -55C to +125C Operating free air temperature range, (TA) (device type 03) . -55C to +60C Storage temperature range, (TSTG) . -65C to

13、+150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +300C ESD ratings: HBM +3000 V CDM +1500 V MM +100 V Package dissipation ratings: Package JC(C/W) JA 7/ (C/W) Case X 38.3 97.5 Case Y 4/ 4.7 58.4 1.4 Recommended operating conditions. Supply voltage: Maximum dual supply 7.5 V Singl

14、e supply +4.5 V to +15.0 V Operating free air temperature range, (TA) (device type 01 and 02) -55C to +125C Operating free air temperature range, (TA) (device type 03) -55C to +60C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Sem

15、iconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3/ Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions fo

16、r extended periods may affect device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 4/ The devices on this drawing may incorporate a thermal pad on the underside of the chip. This act as a hea

17、tsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. Refer to the manufacturer for more information about utilizing the thermally enhanced packag

18、e. 5/ The absolute maximum temperature under any condition is limited by the constraints of the silicon process. 6/ Long term high temperature storage and/or extended used at maximum recommended operating conditions may result in a reduction of overall device life. See figure 3 for additional inform

19、ation on thermal derating. 7/ This data was taken using JEDEC standard high-K test PCB. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 4 3. REQUI

20、REMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the

21、 manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The

22、 design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Wirebond life versus temperature. Wirebo

23、nd life versus temperature shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 5 TABLE I. Electrical performance charac

24、teristics. 1/ Test Test condition VS= 5.0 V, G = +1 Rf = Rg= 1 k, RL= 399 Single ended input unless otherwise noted Device type: 2/ Limits Unit Min/ Typ/ Max Typ Over temperature 3/ 25C 25C -55C to +125C OR -55C to +60C AC Performance Small signal bandwidth G = +1, PIN= -20 dBm, Rf= 392 370 MHz Typ

25、G = +2, PIN= -30 dBm, Rf= 1 k 175 G = +5, PIN= -30 dBm, Rf= 1.3 k 70 G = +10, PIN= -30 dBm, Rf= 1.3 k 30 Gain bandwidth product G +10 300 Bandwidth for 0.1 dB flatness PIN= -20 dBm 150 Large signal bandwidth VP= 2 V 220 Slew rate 4 VPPStep 2800 V/s Rise time 2 VPPStep 0.8 ns Fall time 2 VPPStep 0.6

26、Setting time to 0.01% VO= 4 VPP8.3 Setting time to 0.1% VO= 4 VPP6.3 Harmonic distortion G = +1, VO= 2 VPP2ndharmonic f = 8 MHz -83 dBc f = 30 MHz -74 3rdharmonic f = 8 MHz -97 f = 30 MHz -78 Third order intermodulation distortion VO= 2 VPP, fc = 30 MHz, Rf= 392 , 200 kHz tone spacing -94 Third orde

27、r output intercept point fc = 30 MHz, Rf= 392 , Referenced to 50 , 52 dBm Input voltage noise f 1 MHz 6.8 nV/ Hz Input current noise f 100 kHz 1.7 pA/ Hz Overdrive recovery time Overdrive = 5.5 V 75 ns DC performance Open loop voltage gain 55 52 48 dB Min Input offset voltage VOD= 4 V, VOCM= 0 V -1

28、6 7 mV Max Average offset voltage drift 10 V/C Typ Input bias current 4 4.6 5.4 A Max Average bias current drift 10 nA/C Typ Input offset current 0.5 1 2 A Max Average offset current drift 40 nA/C Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

29、hout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Test condition VS= 5.0 V, G = +1 Rf = Rg= 1 k, RL= 399 Single ended input unless otherwise noted Devi

30、ce type: 2/ Limits Unit Min/ Typ/ Max Typ Over temperature 3/ 25C 25C -55C to +125C OR -55C to +60C Input Common mode input range 4.0 3.7 3.4 V Min Common mode rejection ratio 80 74 70 dB Min Input impedance VICM= 0.5 V, VOCM= 0 V 107| 1 | pF Typ Output Differential output voltage swing RL= 399 8 7.

31、6 7.4 V Min Differential output current drive RL= 20 120 110 100 mA Min Output balance error PIN= -20 dBm, f = 100 kHz -58 dB Typ Closed loop output impedance (single ended) f = 1 MHz 0.1 Typ Output Common Mode Voltage control Small signal bandwidth RL= 400 180 MHz Typ Slew rate 2 VPPstep 87 V/s Typ

32、 Minimum gain 1 0.98 0.98 V/V Min Maximum gain 1 1.02 1.02 V/V Max Common mode offset voltage +2 7.5 9.9 mV Max Input bias current VOCM= 2.5 V 100 150 170 A Max Input voltage range 4 3.7 3.4 V Min Input impedance 25 | 1 k | pF Typ Maximum default voltage VOCMleft floating 0 0.05 0.1 V Max Minimum de

33、fault voltage VOCMleft floating 0 -0.05 -0.1 V Min Power supply Specified operating voltage 5 7.5 7.5 V Max Maximum quiescent current 23 28 34 mA Max Minimum quiescent current 23 16 10 mA Min Power supply rejection (PSRR) VS+ = 4 V to 5 V, VS- = -5 V to -4 V 80 76 70 dB Min Power down (device type 0

34、1 only) Enable voltage threshold Device enabled ON above -2.9 V -2.9 V Min Disable voltage threshold Device disabled OFF below -4.3 V -4.3 V Max Power down quiescent current 800 1000 1200 A Max Input bias current 200 240 260 A Max Input impedance 50 | 1 k | pF Typ Turn on time delay 1000 ns Typ Turn

35、 off time delay 800 ns Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 7 TABLE I. Electrical performance characteri

36、stics.- Continued. 1/ Test Test condition VS= 5.0 V, G = +1 Rf = Rg= 1 k, RL= 399 Single ended input unless otherwise noted Device type: 2/ Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C OR -55C to +60C AC Performance Small signal bandwidth G = +1, PIN= -20 dBm, Rf= 392 320 MHz

37、 Typ G = +2, PIN= -30 dBm, Rf= 1 k 160 G = +5, PIN= -30 dBm, Rf= 1.3 k 60 G = +10, PIN= -30 dBm, Rf= 1.3 k 30 Gain bandwidth product G +10 300 Bandwidth for 0.1 dB flatness PIN= -20 dBm 180 Large signal bandwidth VP= 1 V 200 Slew rate 2 VPPStep 1300 V/s Rise time 2 VPPStep 0.6 ns Fall time 2 VPPStep

38、 0.8 Setting time to 0.01% VO= 2 V Step 13.1 Setting time to 0.1% VO= 2 V Step 8.3 Harmonic distortion VO= 2 VPP2ndharmonic f = 8 MHz -81 dBc f = 30 MHz -60 3rdharmonic f = 8 MHz -74 f = 30 MHz -62 Input voltage noise f 1 MHz 6.8 nV/ Hz Input current noise f 100 kHz 1.6 pA/ Hz Overdrive recovery tim

39、e Overdrive = 5.5 V 75 ns DC performance Open loop voltage gain 54 51 48 dB Min Input offset voltage VOD= 1 V, VOCM= 2.5 V -0.6 5 6.5 mV Max Average offset voltage drift 10 V/C Typ Input bias current 4 4.6 5.2 A Max Average bias current drift 10 nA/C Typ Input offset current 0.5 0.7 1.2 A Max Averag

40、e offset current drift 20 nA/C Typ Input Common mode input range 1 / 4 1.3 / 3.7 1.6 / 3.4 V Min Common mode rejection ratio 80 74 60 dB Min Input impedance VICM= 2.25 V to 2.75 V, VOCM= 2.5 V 107| 1 | pF Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permi

41、tted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05608 REV B PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Test condition VS= 5.0 V, G = +1 Rf = Rg= 1 k, RL= 399 Single ended input unless otherwise no

42、ted Device type: 2/ Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C OR -55C to +60C Output Differential output voltage swing RL= 399 , Referenced to 2.5 V 3.3 2.8 2.6 V Min Differential output current drive RL= 20 100 90 80 mA Min Output balance error PIN= -20 dBm, f = 100 kHz -

43、58 dB Typ Closed loop output impedance (single ended) f = 1 MHz 0.1 Typ Output Common Mode Voltage control Small signal bandwidth RL= 400 180 MHz Typ Slew rate 2 VPPstep 80 V/s Typ Minimum gain 1 0.98 0.98 V/V Min Maximum gain 1 1.02 1.02 V/V Max Common mode offset voltage 2 6.7 9.2 mV Max Input bia

44、s current VOCM= 2.5 V 1 2 3 A Max Input voltage range 1 / 4 1.2/3.8 1.3/3.7 V Min Input impedance 25 | 1 k | pF Typ Maximum default voltage VOCMleft floating 2.5 2.55 2.6 V Max Minimum default voltage VOCMleft floating 2.5 2.45 2.4 V Min Power supply Specified operating voltage 5 15 15 V Max Maximum

45、 quiescent current 20 25 31 mA Max Minimum quiescent current 20 15 8 mA Min Power supply rejection (PSRR) VS+ = 4.5 V to 5.5 V 75 72 66 dB Min Power down (device type 01 only) Enable voltage threshold Device enabled ON above -2.1 V 2.1 V Min Disable voltage threshold Device disabled OFF below 0.7 V

46、0.7 V Max Power down quiescent current 600 800 1200 A Max Input bias current 100 125 140 A Max Input impedance 50 | 1 k | pF Typ Turn on time delay 1000 ns Typ Turn off time delay 800 ns Typ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product per

47、formance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Device type 01 and 02 operate at TA= -55C to +125C and device type 03 operates at TA= -55C to +60C. 3/ See maximum die temperature to prevent oscillation section in the Application Information from manufacturer data. Provided by IHSNot for ResaleNo reproduction or

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1