1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 12-01-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, SINGLE POSITIVE-EDGE-TRIGGERED D-T
3、YPE FLIP-FLOP, MONOLITHIC SILICON YY MM DD 05-10-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05621 REV A PAGE 1 OF 10 AMSC N/A 5962-V023-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COL
4、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single positive-edge-triggered D-type flip-flop microcircuit, with an operating temperature range of -55C to +115C. 1.2 Vendor Item Drawing
5、 Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05621 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See
6、 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC1G79-EP Single positive-edge-triggered D-type flip-flop 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 JEDEC MO-203 Plastic small o
7、utline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply vol
8、tage range, (VCC) . -0.5 V to +6.5 V Input voltage range, (VI) . -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high impedance or power-off state, (VO) -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high or slow state, (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp cur
9、rent, (IIK) (VI 0) -50 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance (JA) . 252C/W 4/ Storage temperature range, (TSTG) . -65C to +150C _ 1/ Stresses beyond those listed under “absolute max
10、imum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended per
11、iods may affect device reliability. 2/ The input and output negative voltage ratings may exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in recommended operating conditions. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Pro
12、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 3 1.4 Recommended operating conditions. 1/ Supply voltage, (VCC): Minimum operating . +1.65 V Minimum
13、 data retention only +1.5 V Minimum high level input voltage, (VIH): VCC= 1.65 V to 1.95 V +0.65 x VCCVCC= 2.3 V to 2.7 V +1.7 V VCC= 3 V to 3.6 V . +2 V VCC= 4.5 V to 5.5 V +0.7 x VCCMaximum low level input voltage, (VIL): VCC= 1.65 V to 1.95 V +0.35 x VCCVCC= 2.3 V to 2.7 V +0.7 V VCC= 3 V to 3.6
14、V . +0.8 V VCC= 4.5 V to 5.5 V +0.3 x VCCInput voltage range, (VI) 0 V to 5.5 V Output voltage range, (VO) 0 V to VCCMaximum high level output current, (IOH): VCC= 1.65 V . -4 mA VCC= 2.3 V . -8 mA VCC= 3 V -16 mA VCC= 3 V . -24 mA VCC= 4.5 V . -32 mA Maximum low level output current, (IOL): VCC= 1.
15、65 V . 4 mA VCC= 2.3 V . 8 mA VCC= 3 V 16 mA VCC= 3 V . 24 mA VCC= 4.5 V . 32 mA Maximum Input transition rise or fall rate (t/v): VCC= 1.8 V 0.15 V, 2.5 V 0.2 V 20 ns/V VCC= 3.3 V 0.3 V . 10 ns/V VCC= 5 V 0.5 V 5 ns/V Operating free air temperature, (TA) -55C to +115C 2. APPLICABLE DOCUMENTS JEDEC
16、SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Soli
17、d State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) _ 1/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY
18、 CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifi
19、er C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
20、 as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The term
21、inal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Load circuit and switching waveforms. The load circuit and switching waveforms shall be as specified in
22、figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -55C TA +11
23、5C unless otherwise specified VCCLimits Unit Min Max High level output voltage VOHIOH= -100 A 1.65 V to 5.5 V VCC 0.1 V IOH= -4 mA 1.65 V 1.2 IOH= -8 mA 2.3 V 1.9 IOH= -16 mA 3 V 2.4 IOH= -24 mA 2.3 IOH= -32 mA 4.5 V 3.8 Low level output voltage VOLIOL= 100 A 1.65 V to 5.5 V 0.1 IOL= 4 mA 1.65 V 0.4
24、5 IOL= 8 mA 2.3 V 0.3 IOL= 16 mA 3 V 0.4 IOL= 24 mA 0.55 IOL= 32 mA 4.5 V 0.55 Input current, CLK or D inputs IIVI= 5.5 V or GND 0 to 5.5 V 10 A Input/output power off leakage current IoffVIor VO= 5.5 V 0 V 10 A Quiescent supply current ICCVI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 A Quiescent suppl
25、y current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 5.5 V 500 A Input capacitance CiVI= VCCor GND, TA= 25C 3.3 V 4 Typ pF Clock frequency fclockSee figure 5. 1.8 V 0.15 V 160 MHz 2.5 V 0.2 V 160 3.3 V 0.3 V 160 5 V 0.5 V 160 Pulse duration, CLK high or low twSee figure 5. 1.8
26、 V 0.15 V 2.5 ns 2.5 V 0.2 V 2.5 3.3 V 0.3 V 2.5 5 V 0.5 V 2.5 Setup time, before CLK tsu Data high See figure 5. 1.8 V 0.15 V 2.2 ns 2.5 V 0.2 V 1.4 3.3 V 0.3 V 1.3 5 V 0.5 V 1.2 Data low See figure 5. 1.8 V 0.15 V 2.6 2.5 V 0.2 V 1.4 3.3 V 0.3 V 1.3 5 V 0.5 V 1.2 See footnotes at end of table. Pro
27、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions -55C TA +115
28、C unless otherwise specified VCCLimits Unit Min Max Hold time, data after CLK th See figure 5. 1.8 V 0.15 V 0.3 ns 2.5 V 0.2 V 0.4 3.3 V 0.3 V 1 5 V 0.5 V 0.5 Maximum frequency fmaxSee figure 5. 1.8 V 0.15 V 160 MHz 2.5 V 0.2 V 160 3.3 V 0.3 V 160 5 V 0.5 V 160 Propagation delay time, from input CLK
29、 to output Q tpdSee figure 5. 1.8 V 0.15 V 3.9 10.1 ns 2.5 V 0.2 V 2 7 3.3 V 0.3 V 1.7 5 5 V 0.5 V 1 4.5 Power dissipation capacitance CpdTA= 25C f = 10 MHz 1.8 V 26 Typ pF 2.5 V 26 Typ 3.3 V 27 Typ 5.0 V 30 Typ 1/ Testing and other quality control techniques are used to the extent deemed necessary
30、to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or desig
31、n. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 7 Case X 1 35 4Db5 PLS0.10 ME E1AA1SEATINGPLANE0.10SEEDETAIL ADETAIL A0-8GAGEPLANEL1cLeDimensio
32、ns Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .031 .043 0.80 1.10 E .043 .055 1.10 1.40 A1 .000 .004 0.00 0.10 E1 .070 .094 1.80 2.40 b .006 .012 0.15 0.30 e .025 BSC 0.65 BSC c .005 NOM 0.13 NOM L .010 .018 0.26 0.46 D .072 .084 1.85 2.15 L1 .006 TYP 0.15
33、TYP Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. Falls within JEDEC MO-203. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without
34、license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 8 Case outline: X Terminal number Terminal name 1 D 2 CLK 3 GND 4 Q 5 VCCFIGURE 2. Terminal connections. FIGURE 3. Logic diagram. Inputs Output Q CLK D L H L X H L Q0FIGURE 4.
35、 Function Table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 9 Notes: 1. CLincludes probe and test fixture capacitance. 2. Waveform 1 is for an
36、 output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by generators having following cha
37、racteristics: PRR 10 MHz, ZO= 50 . 4. The outputs are measured one at a time with one transition per measurement. 5. tPLZand tPHZare the same tdis. 6. tPZLand tPZHare the same ten. 7. tPLHand tPHLare the same tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circ
38、uit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05621 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufactur
39、er is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION
40、FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 mi
41、nimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supp
42、ly. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-side marking 2/ V62/
43、05621-01XE 01295 SN74LVC1G79WDCKREP CR_ 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ The actual top-side marking has one additional character that designates the assembly/test site. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
