1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Changes were made to the following tests under Table I; quiescent current, hysteresis voltage, Internally set-free running frequency range, externally set-free running frequency range, input bias current, VSENSE pin, internal slow start time, charge current,
2、SS/ENA pin, discharge current, SS/ENA pin, output saturation voltage PWRGD pin, leakage current PWRGD, current limit trip point, and power MOSFET switches. Changes were also made to footnote 7/ under Table I, note under figure 1, and BOOT description under figure 2. Updating document to current requ
3、irements. - ro 10-11-08 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 1
4、0 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, 3 V to 6 V INPUT, 6 A OUTPUT SYNCHRONOUS PULSE WIDTH MODULATOR, MONOLITHIC SILICON 05-10-05 APPROVED B
5、Y RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05622 REV A PAGE 1 OF 15 AMSC N/A 5962-V009-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV
6、A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3 V to 6 V input, 6 A output synchronous pulse width modulator microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacture
7、rs PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05622 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Devic
8、e type Generic Circuit function Output voltage 01 TPS54610-EP 3 V to 6 V input, 6 A output Adjustable down to 0.9 V synchronous pulse width modulator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 MO-153 Plastic small
9、 outline package with a thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for Res
10、aleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Input voltage range (VI): VIN, SS/ENA, FSEL pins . -0.3 V to 7 V RT pin -0.3 V to 6 V VSE
11、NSE pin . -0.3 V to 4 V BOOT pin . -0.3 V to 17 V Output voltage range (VO): VBIAS, COMP, PWRGD pins . -0.3 V to 7 V PH pin -0.6 V to 10 V Source current (IO): PH pin Internally limited COMP, VBIAS pin 6 mA Sink current (IS): PH pin 12 A COMP pin 6 mA SS/ENA, PWRGD pins . 10 mA Voltage differential
12、(AGND to PGND pins) . 0.3 V Operating virtual junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 300C 1.4 Recommended operating conditions. 2/ Input voltage range (VI) 3 V to 6 V Operating virtua
13、l junction temperature range (TJ) -55C to +125C 1.5. Power dissipation rating table. 3/ 4/ Package Thermal impedance junction-to-ambient TA= 25C power rating TA= 70C power rating TA= 85C power rating Case X with solder 18.2C/W 5.49 W 5/ 3.02 W 2.2 W Case X without solder 40.5C/W 2.48 W 1.36 W 0.99 W
14、 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure t
15、o absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the
16、 stated limits. 3/ For more information on the case X (PWP) package, see the manufacturers technical brief SLMA002. 4/ Test board conditions: a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch. b. 1.5 ounce copper traces located on the top of the printed circuit board (PCB). c. 1.5 ounce copper gro
17、und plane on the bottom of the printed circuit board (PCB). d. 0.5 ounce copper ground planes on the 2 internal layers. e. 12 thermal vias (see recommended land pattern section in the applications section of the data sheet). 5/ Maximum power dissipation may be limited by over current protection. Pro
18、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Ap
19、plications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and
20、as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommen
21、ded operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall
22、be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Test circuit. The test circuit shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproductio
23、n or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ 2/ Test Symbol ConditionsTemperature, TJ Device type Limits Unit Min Max Supply voltage
24、 (VIN) section Input voltage range VIN-55C to +125C 01 3 6 V Quiescent current I(Q)fS= 350 kHz, FSEL 0.8 V, RT open, phase pin open -55C to +125C 01 19 mA fS= 550 kHz, FSEL 2.5 V, RT open, phase pin open 25 Shutdown, SS/ENA = 0 V 1.4 Under voltage lock out (UVLO) section Start threshold voltage -55C
25、 to +125C 01 3 V Stop threshold voltage -55C to +125C 01 2.7 V Hysteresis voltage -55C to +125C 01 0.12 V Rising and falling 3/ edge deglitch -55C to +125C 01 2.5 typical s Bias voltage (VBIAS) section Output voltage I(VBIAS)= 0 -55C to +125C 01 2.7 2.95 V Output current 4/ -55C to +125C 01 100 A Cu
26、mulative reference section Accuracy 3/ VREF-55C to +125C 01 0.882 0.9 V Regulation section Line regulation 3/ 5/ IL= 3 A, fS= 350 kHz +125C 01 0.07 %/V IL= 3 A, fS= 550 kHz +125C 0.07 Load regulation 3/ 5/ IL= 0 A to 6 A, fS= 350 kHz +125C 01 0.03 %/A IL= 0 A to 6 A, fS= 550 kHz +125C 0.03 See footn
27、otes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ 2/ Test Symb
28、ol ConditionsTemperature, TJ Device type Limits Unit Min Max Oscillator section Internally set free running frequency FSEL 0.8 V, RT open -55C to +125C 01 270 425 kHz FSEL 2.5 V, RT open 415 662 Externally set free running frequency range RT = 180 k (1 % resistor to AGND) 3/ -55C to +125C 01 245 315
29、 kHz RT = 160 k (1 % resistor to AGND) 285 360 RT = 68 k (1 % resistor to AGND) 3/ 655 773 High level threshold, FSEL pin -55C to +125C 01 2.5 V Low level threshold, FSEL pin -55C to +125C 01 0.8 V Pulse duration, external synchronization, FSEL pin 3/ -55C to +125C 01 50 ns Frequency range, FSEL pin
30、 3/ 6/ -55C to +125C 01 330 700 kHz Ramp valley 3/ -55C to +125C 01 0.75 typical V Ramp amplitude (peak to peak) 3/ -55C to +125C 01 1 typical V Minimum controllable on time 3/ -55C to +125C 01 200 ns Maximum duty cycle 3/ -55C to +125C 01 90% See footnotes at end of table. Provided by IHSNot for Re
31、saleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ 2/ Test Symbol ConditionsTemperature, TJ Device type Limits
32、 Unit Min Max Error amplifier section Error amplifier open loop voltage gain 1 k COMP to AGND 3/ -55C to +125C 01 90 dB Error amplifier unity gain bandwidth Parallel 10 k, 3/ 160 pF COMP to AGND -55C to +125C 01 3 MHz Error amplifier common mode input voltage range Powered by internal low drop out (
33、LDO) regulator 3/ -55C to +125C 01 0 VBIAS V Input bias current, VSENSE pin VSENSE = VREF3/ -55C to +125C 01 60 typical nA Output voltage slew rate (symmetric), COMP 3/ -55C to +125C 01 1 V/s PWM comparator section PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead
34、 time) 10 mV overdrive 3/ -55C to +125C 01 85 ns Slow start / enable section Enable threshold voltage, SS/ENA pin -55C to +125C 01 0.82 1.4 V Enable hysteresis voltage, SS/ENA pin -55C to +125C 01 0.03 typical V Falling edge deglitch, SS/ENA pin 3/ -55C to +125C 01 2.5 typical s Internal slow start
35、time 3/ -55C to +125C 01 2 4.5 ms Charge current, SS/ENA pin SS/ENA = 0 V -55C to +125C 01 2.5 8 A Discharge current, SS/ENA pin SS/ENA = 0.2 V, VI= 2.7 V -55C to +125C 01 1.1 4 mA Power good section Power good threshold voltage VSENSE falling -55C to +125C 01 90 typical %VREFPower good hysteresis v
36、oltage 3/ -55C to +125C 01 3 typical %VREFSee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 8 TABLE I. Electrical per
37、formance characteristics Continued. 1/ 2/ Test Symbol ConditionsTemperature, TJ Device type Limits Unit Min Max Power good section - Continued Power good falling edge deglitch 3/ -55C to +125C 01 35 typical s Output saturation voltage, PWRGD pin I(sink)= 2.5 mA -55C to +125C 01 0.31 V Leakage curren
38、t, PWRGD pin VI= 5.5 V -55C to +125C 01 100 typical nA Current limit section Current limit trip point VI= 3 V 3/ -55C to +125C 01 10 typical A VI= 6 V 3/ 12 typical Current limit leading edge blanking time 3/ -55C to +125C 01 100 typical ns Current limit total response time 3/ -55C to +125C 01 200 t
39、ypical ns Thermal shutdown section Thermal shutdown trip point 3/ -55C to +125C All 135 165 C Thermal shutdown hysteresis 3/ -55C to +125C All 10 typical C Output power MOSFETs - section Power MOSFET switches rDS(on)VI= 6 V 7/ -55C to +125C All 51 m VI= 3 V 7/ 67 1/ Testing and other quality control
40、 techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product per
41、formance is assured by characterization and/or design. 2/ Unless otherwise specified, TJ= -55C to +125C and VI= 3 V to 6 V. 3/ Specified by design. 4/ Static resistive loads only. 5/ Tested using circuit in figure 4. 6/ To ensure proper operation when the RC filter is used between the external clock
42、 and the FSEL pin, the recommended values are R 1 k and C 120 pF. 7/ Matched metal oxide semiconductor field effect transistors (MOSFETs), low side rDS(on)production tested, high side rDS(on)specified by design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
43、m IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 9 Case X FIGURE 1. Case outline . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A
44、CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 10 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.047 - 1.20 A1 0.001 0.005 0.05 0.15 b 0.007 0.011 0.19 0.30 c 0.005 nominal 0.15 nominal D 0.377 0.385 9.60 9.80 e 0.025 BSC 0.65 BSC E 0.169 0.177 4.30 4.50 E1 0.244 0.259 6.20 6.6
45、0 L 0.019 0.029 0.50 0.75 n 28 leads 28 leads NOTE: 1. Controlling dimensions are in millimeter, inch dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch) per side. 3. This package is des
46、igned to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package, manufacturers literature number SLMA002 for information regarding recommended board layout. 4. Falls within JEDEC MO-153. FIGURE 1. Case outline Continued. Provided by IHSNot for Resal
47、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05622 REV A PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol 1 AGND 2 VSENSE 3 COMP 4 PWRGD 5 BOOT 6 PH 7 PH 8 PH 9 PH 10 PH 11 PH 12 PH 13 PH 14 PH 15 PGND 16 PGND 17 PGND 18 PGND 19 PGND 20 VIN 21 VIN 22 VIN 23 VIN 24 VIN 25 VBIAS 26 SS / ENA 27 FSEL 28 RT FIGURE 2. Terminal connections. Provided
