1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02 and case outline Y. - phn 10-01-06 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DEFEN
2、SE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, DUAL 4-A HIGH-SPEED LOW-SLIDE MOSFET DRIVER WITH ENABLE, MONOLITHIC SILICON 07-03-21 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07624 REV A PAGE
3、1 OF 10 AMSC N/A 5962-V016-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirement
4、s of a high performance dual 4-A high-speed low slide MOSFET driver with enable microcircuit, with an extended operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes
5、 an administrative control number for identifying the item on the engineering documentation: V62/07624 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device Generic Circuit function 01 UCC27424-EP Dual 4-A high-speed low slide MOS
6、FET driver with enable 02 UCC27423-EP Dual 4-A high-speed low slide MOSFET driver with enable 1.2.2 Case outline(s). The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 JEDEC MO-187 Plastic small outline package Y 8 JEDEC MS-012 Plastic small outlin
7、e package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or n
8、etworking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VDD) -0.3 V to 16.0 V Maximum output current: OUTA, OUTB: DC, IOUT_DC0.2 A Pulse (0.5 s),
9、 IOUT_PULSE 4.5 A Input voltage range, INA, INB (VIN) -5 V to 6 V or VDD+ 0.3 V 3/ Enable voltage: ENBA, ENBB -0.3 V to 6 V or VDD+ 0.3 V 3/ Power dissipation at TA= 25C: Case outline X . 3 W Case outline Y . 650 mW Junction operating temperature range (TJ) . -55C to +150C Storage temperature range
10、(TSTG) . -65C to +150C Lead temperature (soldering, 10 s) 300C Dissipation Rating Case outline JC (C/W) JA (C/W) Power rating TA= 70C Derating Factor Above TA= 70C X 5/ 4.7 50 to 59 1370 mW 4/ 17.1 mW/C 4/ Y 42 84 to 160 344 to 655 mW 6/ 7/ 6.25 to 11.9 mW/C 6/ 7/ 2. APPLICABLE DOCUMENTS JEDEC PUB 9
11、5 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanen
12、t damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabil
13、ity. 2/ All voltages are with respect to GND. Current are positive into and negative out of the specified terminal. 3/ whichever is larger. 4/ 150C operating junction temperature is used for power rating calculations. 5/ The package X is not directly connected to any leads of the package. However, i
14、t is electrically and thermally connected to the substrate, which is the ground of the device. 6/ The range of value indicates the effect of PC board. These values are intended to give system designer an indication of the best and worst case conditions. In general, the system designer should attempt
15、 to use lager traces on the PC board, where possible, in order to spread the heat away from the device more effectively. For more information see manufacturer data. 7/ 125C operating junction temperature is used for power rating calculations. Provided by IHSNot for ResaleNo reproduction or networkin
16、g permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Man
17、ufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating cond
18、itions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown
19、in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.5.3 Function table. The function table shall be as specified on figure 3. 3.5.3 Block diagram. The functional block diagram shall be as specified on figure 4. 3.5.4 Switching waveform for
20、 Inverting and Noninverting driver. The switching waveforms for inverting and noninverting driver shall be as specified on figure 5. 3.5.5 Switching waveform for enable to output. The switching waveforms for enable to output shall be as specified on figure 6. Provided by IHSNot for ResaleNo reproduc
21、tion or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 4.5 V VDD 15 V -55C TA= TJ 125C unless otherwise specified
22、 Limits Unit Device type 01 Device type 02 Min Max Min Max Input (INA, INB) Logic 1 input threshold VIN_H2 2 V Logic 0 input threshold VIN_L1 1 V input current 0 V VIN VDD-10 10 -10 10 A Output (OUTA, OUTB) Output current VDD= 14 V 2/ 3/ 4 Typ 4 Typ AS High level output voltage VOHVOH= VDD VOUT, IOU
23、T= -10 mA 450 450 mV Low level output voltage VOLIOUT= 10 mA 40 40 mV Output resistance high IOUT= -10 mA, VDD= 14 V 4/ TA= 25C 25 35 25 35 TA= full range 18 45 14 45 Output resistance low IOUT= -10 mA, VDD= 14 V 4/ TA= 25C 1.9 2.5 1.9 2.5 TA= full range 1.2 4 0.95 4 Latch up protection 500 500 mA S
24、witching time Rise time (OUTA, OUTB) tRCLOAD= 1.8 nF 2/ 40 40 ns Fall time (OUTA, OUTB) tFCLOAD= 1.8 nF 2/ 40 40 Delay, IN rising (IN to OUT) tD1CLOAD= 1.8 nF 2/ 50 55 Delay IN falling (IN to OUT) tD2CLOAD= 1.8 nF 2/ 45 60 Enable (ENBA, ENBB) High level input voltage VIN_HLOW to HIGH transaction 1.7
25、 2.9 1.7 3.1 V Low level input voltage VIN_LHIGH to LOW transaction 1.1 2.2 1.1 2.3 V Hysteresis 0.10 0.9 0.13 1.1 V Enable impedance RENBLVDD= 14 V, ENBL = GND 75 140 75 160 k Propagation delay time tD3CLOAD= 1.8 nF, See figure 5 2/ 60 60 ns Propagation delay time tD4CLOAD= 1.8 nF, See figure 5 2/
26、150 150 ns Overall Static operating current, VDD= 15 V, ENBA = ENBB = 15 V IDDINA = 0 V INB = 0 V 450 1350 A INB = HIGH 1100 1100 INA = HIGH INB = 0 V 1100 1100 INB = HIGH 1800 900 Disabled, VDD= 15 V, ENBA = ENBB = 0 V INA = 0 V INB = 0 V 450 450 INB = HIGH 700 700 INA = HIGH INB = 0 V 700 700 INB
27、= HIGH 900 900 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the
28、absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Specified by design. Not tested in production. 3/ The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined c
29、urrent from the bipolar and MOSFET transistors. 4/ The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver outputis less than the saturation voltage of the bipolar transist
30、or 5/ The maximum output current depends on the input voltage. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 6 Case X Symbol Millimeters Symbol Mi
31、llimeters Min Max Min Max A 1.07 e 0.65 BSC A1 0.05 0.15 E 2.95 3.05 b 0.25 0.38 E1 4.78 4.98 c 0.15 NOM L 0.41 0.69 D 2.95 3.05 Notes: 1. All liner dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. The
32、package is designed to be soldered to a thermal pad on the board. See manufacturer data for details regarding the exposed thermal pad dimensions. 5. Falls within JEDEC MO-187. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DE
33、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 7 Case Y Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .069 1.75 D .189 .197 4.80 5.00 A1 .004 .010 0.10 0.25 E .150 .157 3.80 4.00 A2 .010 TYP 0.25
34、TYP E1 .228 .244 5.80 6.20 b .012 .020 0.31 0.51 e .050 BSC 1.27 BSC c .005 .010 0.13 0.25 L .016 .050 0.40 1.27 Notes: 1. All liner dimensions are in inch (millimeters). 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold
35、 flash, protrusions, or gate burrs shall not exceed .006 (0.15) per end 4. Body width does not include interlead flash. Interlead flash shall not exceed .017 (0.43) per side. 5. Falls within JEDEC MS-012 variation AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction o
36、r networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 8 Case X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 ENBA 5 OTUB 2 INA 6 VDD 3 GND 7 OUTA 4 INB 8 ENBB FIGURE 2. Termi
37、nal connections. Inputs (VIN_L, VIN_H) Outputs ENBA ENBB INA INB OUTA OUTB H H L L L L H H L H L H H H H L H L H H H H H H L L X X L L FIGURE 3. Function table. FIGURE 4. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY C
38、ENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 9 Note: The 10% and 90% threshold depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of the operation. FIGURE 5. Switching waveform for Inverting
39、and Noninverting driver. Note: The 10% and 90% threshold depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of the operation. FIGURE 6. Switching waveform for enable to output Provided by IHSNot for ResaleNo reproduction or networki
40、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07624 REV PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in t
41、heir internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in
42、accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient cha
43、racteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed a
44、s a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/07624-01XE 01295 UCC27424MDGNREP V62/07624-02YE 01295 UCC27423MDREP 1/ The vendor item drawing establishes
45、an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
