1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CH
2、ECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, DIFFERENTIAL LINE DRIVER, MONOLITHIC SILICON 11-11-01 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07627 REV PAGE 1 OF 15 AMSC N/A 5962-V076-11 Provided by IHSNot for ResaleNo reproduction or networking permitted
3、without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance differential line driver microcircuit, with an operating temperature range of -55C to +
4、125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/07627 - 01 X E Drawing Device type Case outline Lead f
5、inish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN65LVDS31-EP High speed differential line driver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012-AC
6、 Plastic small outline surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for Re
7、saleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4 V 2/ Input voltage range (VI) -0.5 V to VCC+ 0.5 V Continuo
8、us total power dissipation (PD) . See paragraph 1.5. Junction temperature range (TJ) +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +260C Storage temperature range (TSTG) -65C to +150C Thermal resistance, junction to ambient (JC) 36.9C/W Thermal resistance, junction to ambient
9、(JA) 73C/W 1.4 Recommended operating conditions. 3/ Supply voltage range (VCC) . 3 V to 3.6 V High level input voltage (VIH) . 2 V minimum Low level input voltage (VIL) 0.8 V maximum Operating free-air temperature range (TA) . -55C to +125C 1.5 Dissipation ratings. Package Power rating TA 25C Derati
10、ng factor above TA= 25C 4/ Power rating TA= 70C Power rating TA= 85C Power rating TA= 125C Case X 950 mW 7.6 mW/C 608 mW 494 mW 190 mW 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of
11、the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltages, except differential I/O bus voltages, are with respect to the
12、 network ground terminal. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ This is the inverse of the junction to ambi
13、ent thermal resistance when board mounted and with no air flow. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registe
14、red and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the ma
15、nufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 E
16、lectrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Di
17、agrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms an
18、d test circuit shall be as shown in figures 4, 5, 6, and 7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 5 TABLE I. Electrical performance characteristics.
19、 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Differential output voltage magnitude VODRL= 100 , see figure 5 -55C to +125C 01 247 454 mV Change in differential output voltage magnitude between logic states VODRL= 100 , see figure 5 -55C to +125C 01 -50 50 mV Steady state
20、common mode output voltage VOC(SS)See figure 6 -55C to +125C 01 1.125 1.375 V Change in steady state common mode output voltage between logic states VOC(SS)See figure 6 -55C to +125C 01 -50 50 mV Peak to peak common mode output voltage VOC(PP)See figure 6 -55C to +125C 01 150 mV Supply current ICCVI
21、= 0.8 V or 2 V, enabled, no load -55C to +125C 01 20 mA VI= 0.8 V or 2 V, enabled, RL= 100 35 VI= 0 or VCC, disabled 1 High level input current IIHVIH= 2 V -55C to +125C 01 20 A Low level input current IILVIL= 0.8 V -55C to +125C 01 10 A Short circuit output current IOSVO(Y)or VO(Z)= 0 -55C to +125C
22、 01 -24 mA VOD= 0 12 High impedance output current IOZVO= 0 or 2.4 V -55C to +125C 01 1 A Power off output current IO(OFF)VCC= 0, VO= 2.4 V -55C to +125C 01 4 A Input capacitance CINVCC= 3.3 V +25C 01 3 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network
23、ing permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Propagation delay time, low to h
24、igh level output tPLHRL= 100 , CL= 10 pF, see figure 5 -55C to +125C 01 0.5 4 ns Propagation delay time, high to low level output tPHLRL= 100 , CL= 10 pF, see figure 5 -55C to +125C 01 1 4.5 ns Differential output signal rise time ( 20% to 80% ) trRL= 100 , CL= 10 pF, VCC= 3.3 V, see figure 5 +25C 0
25、1 0.5 typical ns Differential output signal fall time ( 80% to 20% ) tfRL= 100 , CL= 10 pF, VCC= 3.3 V, see figure 5 +25C 01 0.5 typical ns Pulse skew ( tPHL tPLH) tsk(p)RL= 100 , CL= 10 pF, see figure 5 -55C to +125C 01 0.6 ns Channel to channel 2/ output skew tsk(o)RL= 100 , CL= 10 pF, see figure
26、5 -55C to +125C 01 0.8 ns Propagation delay time, high impedance to high level output tPZHSee figure 7 -55C to +125C 01 17 ns Propagation delay time, high impedance to low level output tPZLSee figure 7 -55C to +125C 01 17 ns Propagation delay time, high level to high impedance output tPHZSee figure
27、7 -55C to +125C 01 18 ns Propagation delay time, low level to high impedance output tPLZSee figure 7 -55C to +125C 01 17 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not nece
28、ssarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ tsk(o)is the maximum delay time difference between drivers on the same device. Pro
29、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 7 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic
30、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 8 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.069 - 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.386 0.394 9.80 10.00 E 0.150 0.157
31、 3.80 4.00 E1 0.228 0.244 5.80 6.20 e 0.050 BSC 1.27 BSC L 0.016 0.050 0.40 1.27 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burr
32、s shall not exceed 0.006 inch (0.15 mm) each side. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) each side. 4. Falls within reference to JEDEC MS-012-AC. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo repro
33、duction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol 1 1A 2 1Y 3 1Z 4 G 5 2Z 6 2Y 7 2A 8 GND 9 3A 10 3Y 11 3Z 12 G 13 4Z 14 4Y 15 4A 16
34、VCCFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 10 INPUT ENABLES OUTPUTS A G G Y Z H H X H L L H X L H H X L H L L X L L H
35、X L H Z Z Open H X L H Open X L L H H = High level L = Low level X = Irrelevant Z = high impedance (off) FIGURE 3. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V
36、62/07627 REV PAGE 11 FIGURE 4. Voltage and current definitions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 12 NOTES: 1. All input pulses are supplied by
37、a generator having the following characteristics: tror tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. 2. CLincludes instrumentation and fixture capacitance within 6 mm of the device under test. FIGURE 5. Timing waveforms and test circuit for the differential output signal.
38、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 13 NOTES: 1. All input pulses are supplied by a generator having the following characteristics: tror tf 1 ns,
39、pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. 2. CLincludes instrumentation and fixture capacitance within 6 mm of the device under test. 3. The measurement of VOC(PP)is made on test equipment with a -3 dB bandwidth of at least 300 MHz. FIGURE 6. Timing waveforms and test circuit f
40、or the driver common mode output voltage. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 14 NOTES: 1. All input pulses are supplied by a generator having the
41、 following characteristics: tror tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns. 2. CLincludes instrumentation and fixture capacitance within 6 mm of the device under test. FIGURE 7. Timing waveforms and test circuit for enable / disable. Provided by IHSNot for ResaleNo rep
42、roduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07627 REV PAGE 15 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as ind
43、icated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking s
44、hall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the
45、salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be
46、construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top siding marking Vendor part number 2/ 3/ V62/07627-01XE 01295 LVDS31EP SN65LVDS31MDTEP 1/ The vendor item drawing es
47、tablishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see manufacturers website at . 3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available at CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Fo
