1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 04. - PHN 08-02-05 Thomas M. Hess B Correct operating temperature for device type 04 in section 1.4. - phn 08-04-22 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV A PAGE 62 63 64 REV PAGE 40 41 42 43 44 45 46
2、47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 REV A PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV B A B A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990
3、http:/www.dscc.dla.mil Original date of drawing CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, VIDEO/IMAGING FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07644 YY MM DD 07-10-01 REV B PAGE 1 OF 64 AMSC N/A 5962-V0
4、48-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance
5、Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +85C (devices type 01), an operating temperature range of -40C to +105C (device type 02 and 03), and an extended operating temperature range of -55C to +105C (device type 04). 1.2 Vendor Item Drawing Ad
6、ministrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/07644 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.
7、2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Clock Rate Circuit function 01 SM320DM642-EP 720 MHz Video/Imaging fixed point digital signal Processor 02 SM320DM642-EP 600 MHz Video/Imaging fixed point digital signal Processor 03 SM320DM642-EP 500 MHz Video/Imaging fixed point digital
8、 signal Processor 04 SM320DM642-EP 720 MHz Video/Imaging fixed point digital signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 548 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or o
9、ther lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Prov
10、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV B PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage ranges: (CVDD) . -0.3 V to +1.8 V 3/ (DVDD) -0.3 V t
11、o +4.0 V 3/ Input voltage ranges: (VI), (except PCI) . -0.3 V to +4.0 V (VIP), (PCI) . -0.5 V to DVDD+ 0.5 V Output voltage ranges: (VO) (except PCI) -0.3 V to +4.0 V (VOP), (PCI) -0.5 V to DVDD+ 0.5 V Operating case temperature ranges, (TC): Device type 01 -40C to +85C Device type (A version) (A-02
12、, A-03) -40C to +105C Device type 04 -55C to +105C Storage temperature range, (TSTG) . -65C to +150C Package temperature cycling: Temperature range . -40C to +125C Number of cycles 500 1.4 Recommended operating conditions. Supply voltage, core (CVDD) (device type 03) +1.14 V to +1.26 V 4/ Supply vol
13、tage, core (CVDD) (device type A-03, A-02, 02 and 01). +1.36 V to +1.44 V 4/ Supply voltage, I/O (DVDD) . +3.14 V to +3.46 V Supply ground, (VSS) 0 V Minimum high level input voltage, (VIH) (except PCI) . +2.0 V Maximum low level input voltage, (VIL) (except PCI) +0.8 V Input voltage, (VIP) (PCI) .
14、-0.5 V to DVDD+ 0.5 V High level input voltage (VIHP) (PCI) 0.5DVDDto DVDD+ 0.5 V Low level input voltage, (VILP) (PCI) .-0.5 V to 0.3DVDDMaximum voltage during overshoot/undershoot . -1.0 V to 4.3 V 5/ Operating case temperature (TC): Device type 01: . -40C to +85C Device type: A Version (A-02 and
15、A-03) . -40C to +105C Device type 04: . -55C to +105C 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recomme
16、nded operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. 4/ Future variants of these devices may operate at voltage ranging from 0.9 V to 1.4 V to provide a range of sys
17、tem power/performance options. Manufacturer highly recommends that users design in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35V, 1.4 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configurat
18、ion modifications. Not incorporating a flexible supply may limit the systems ability to easily adapt future versions of these devices. 5/ The absolute maximum ratings should not be exceeded for more than 30% of the cycle period. Provided by IHSNot for ResaleNo reproduction or networking permitted wi
19、thout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV PAGE 4 1.4 Recommended operating conditions Continued. Thermal resistance characteristics case X: C/W Air flow (m/s) 1 Junction to case, RJC3.3 N/A 2 Junction to board, RJB7.92
20、 N/A 3 18.2 0.00 4 15.3 0.5 5 13.7 1.0 6 Junction to free air, RJA12.2 2.0 7 0.37 0.0 8 0.47 0.5 9 0.57 1.0 10 Junction to package top, PsiJT0.7 2.00 11 11.4 0.00 12 11 0.5 13 10.7 1.0 14 Junction to board PsiJB10.2 2.00 m/s = meter per second 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Stan
21、dard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufactur
22、ers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrica
23、l characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams.
24、3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Test load circuit for AC timing measurement. The tes
25、t load circuit for AC timing measurements shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 5-58. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHI
26、O SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Test conditions 2/ Device type Min Max Unit High level output voltage (except PCI) VOHDVDD= Min, IOH= Max 2.4 High level output voltage (PCI) VOHPIOHP= -0.5 mA, DVDD= 3.3
27、 V 0.9DVDD 3/ Low level output voltage (except PCI) VOLDVDD= Min, IOL= Max 0.4 Low level output voltage (PCI) VOLPIOLP= 1.5 mA, DVDD= 3.3 V 0.1DVDD 3/ V VI= VSSto DVDDno opposing internal resistor 1 VI= VSSto DVDDopposing internal pullup resistor 4/ 50 150 Input current (except PCI)dc IIVI= VSSto DV
28、DDno opposing internal pulldown resistor 4/ -150 -50 Input leakage current (PCI) 5/ IIP0 VIP DVDD= 3.3 V, 10 A EMIF, CLKOUT4, CLKOUT6, EMUx -8 Video Ports, Timer, TDO, GPIO (Excluding GP015:9, 2, 1), McBSP -4 High level output current IOHPCI/HPI -0.5 3/ EMIF, CLKOUT4, CLKOUT6, EMUx 16 Video Ports, T
29、imer, TDO, GPIO (Excluding GP015:9, 2, 1), McBSP 48 SCL0 and SDA0 3 Low level output current IOLPCI/HPI 1.5 3/ mA Off state output current IOZVO= DVDDor 0 V 10 A CVDD= 1.4 V, CPU clock = 720 MHz 1090 Typ CVDD= 1.4 V, CPU clock = 600 MHz 890 Typ Core supply current 6/ ICDDCVDD= 1.2 V, CPU clock = 500
30、 MHz 620 Typ DVDD= 3.3 V, CPU clock = 720 MHz 6/ 210 Typ DVDD= 3.3 V, CPU clock = 600 MHz 6/ 210 TyI/O supply current 6/ IDDDDVDD= 3.3 V, CPU clock = 500 MHz 6/ 165 Typ mA Input capacitance CI10 Typ Output capacitance COAll 10 Typ pF See footnotes at end of table. Provided by IHSNot for ResaleNo rep
31、roduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. Limits No. Test Symbol Test conditions 2/ Device types: All Min Max Unit
32、 EXTERNAL INTERRUPTS ELECTRICAL DATA/TIMMING Timing requirements for external interrupts 7/ Width of the NMI interrupt pulse low 4P 1 Width of the EXT_INT interrupt pulse low tw(ILOW)8P Width of the NMI interrupt pulse high 4P 2 Width of the EXT_INT interrupt pulse high tw(IHIGH)See figure 7 8P ns R
33、ESET ELECTRICAL DATA/TIMMING Timing requirements for reset 1 Width of the RESET pulse tw(RST)250 s 16 Setup time, boot configuration bits valid before RESET high 8/ tsu(boot)4E or 4C 9/ 17 Hold time, boot configuration bits valid after RESET high 8/ th(boot)4P 7/ 18 Setup time, PCLK active before RE
34、SET high 10/ tsu(PCLK-RSTH)See figure 8 32N ns Switching characteristics over recommended operating conditions during Reset 7/ 11/ 12/ 2 Delay time, RESET low to AECLKIN synchronized internally td(RSTL-ECKI)2E 3P+20E 3 Delay time, RESET high to AECLKIN synchronized internally td(RSTH-ECKI)8P+20E 4 D
35、elay time, RESET low to AECLKOUT1 high impedance td(RSTL-ECKO1HZ)2E 5 Delay time, RESET high to AECLKOUT1 valid td(RSTL-ECKO1V)8P+20E 6 Delay time, RESET low to EMIF Z high impedance td(RSTL-EMIFZHZ)2E 3P+4E 7 Delay time, RESET high to EMIF Z valid td(RSTL-EMIFFZV)16E 8P+20E 8 Delay time, RESET low
36、to EMIF high group invalid td(RSTL-EMIFHIV)2E 9 Delay time, RESET high to EMIF high group valid td(RSTL-EMIFHV)8P+20E 10 Delay time, RESET low to EMIF low group invalid td(RSTL-EMIFLIV)2E 11 Delay time, RESET high to EMIF low group invalid td(RSTL-EMIFLV)8P+20E 12 Delay time, RESET low to low group
37、invalid td(RSTL-LOWIV)0 13 Delay time, RESET high to low to group valid td(RSTL-LOWV)11P 14 Delay time, RESET low to Z group high impedance td(RSTL-ZHZ)0 15 Delay time, RESET high to Z group valid td(RSTL-ZV)See figure 8 2P 8P ns See footnotes at end of table. Provided by IHSNot for ResaleNo reprodu
38、ction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. Limits PLL Mode x12 PLL Mode x6 x1 (Bypass) Unit No. Test Symbol Test cond
39、itions 2/ Min Max Min Max Min Max CLOCK PLL ELECTRICAL DATA/TIMING (INPUT/OUTPUT CLOCKS) Timing requirements for CLKIN for device type 03 13/ 14/ 15/ 1 Cycle time, CLKIN tc(CLKIN)24 33.3 13.3 33.3 13.3 33.3 2 Pulse duration, CLKIN high tw(CLKINH)0.45C 0.45C 0.45C 3 Pulse duration, CLKIN low tw(CLKIN
40、L)0.45C 0.45C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 1 5 Period jitter, CLKIN tJ(CLKIN)See figure 10 0.02C 0.02C 0.02C ns Timing requirements for CLKIN for device type 02 13/ 14/ 15/ 1 Cycle time, CLKIN tc(CLKIN)20 33.3 13.3 33.3 13.3 33.3 2 Pulse duration, CLKIN high tw(CLKINH)0.45C 0.45C 0.45
41、C 3 Pulse duration, CLKIN low tw(CLKINL)0.45C 0.45C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 1 5 Period jitter, CLKIN tJ(CLKIN)See figure 10 0.02C 0.02C 0.02C ns Timing requirements for CLKIN for device type 01and 04 13/ 14/ 15/ 1 Cycle time, CLKIN tc(CLKIN)16.6 33.3 13.3 33.3 13.3 33.3 2 Pulse d
42、uration, CLKIN high tw(CLKINH)0.45C 0.45C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.45C 0.45C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 1 5 Period jitter, CLKIN tJ(CLKIN)See figure 10 0.02C 0.02C 0.02C ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking
43、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07644 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. Limits CLKMODE = X1, X6, X12 No. Test Symbol Test conditions 2/ Device type: All Min Max Unit C
44、LOCK PLL ELECTRICAL DATA/TIMING (INPUT/OUTPUT CLOCKS) CONTINUED Switching characteristics for CLKOUT4 7/ 13/ 16/ 1 Pulse duration, CLKOUT4 high tw(CKO4H)2P-0.7 2P+0.7 2 Pulse duration, CLKOUT4 low tw(CKO4L)2P+03 Transaction time, CLKOUT4 tt(CKO4)See figure 11 1 ns Switching characteristics for CLKOU
45、T6 7/ 13/ 16/ 1 Pulse duration, CLKOUT6 high tw(CKO6H)3P-0.7 3P+0.7 2 Pulse duration, CLKOUT6 low tw(CKO6L)3P+03 Transaction time, CLKOUT6 tt(CKO6)See figure 12 1 ns Timing requirements for ECLKIN for EMIFA 7/ 13/ 17/ 1 Cycle time, AECLKIN tc(EKI)6 18/ 16P 2 Pulse duration, AECLKIN high tw(EHIH)2.7
46、3 Pulse duration, AECLKIN low tw(EKIL)4 Transaction, AECLKIN tt(EKI)3 5 Perid jitter, AECLKIN tJ(EKI)See figure 13 0.02E ns Switching characteristics for AECLKOUT1 for EMIFA modules 13/ 17/ 19/ 1 Pulse duration, AECLKOUT1 high tw(EKO1H)EH-0.7 EH+0.7 2 Pulse duration, AECLKOUT1 low tw(EKO1L)EL-0.7 EL
47、+0.7 3 Transition time, AECLKOUT1 tt(EKO1)1 4 Delay time, AECLKIN high to AECLKOUT1 high td(EKIH-EKO1H)1 8 5 Delay time, AECLKIN low to AECLKOUT1 low td(EKIL-EKO1L)See figure 14 1 8 ns Switching characteristics for ECLKOUT2 for EMIFA and EMIFB modules 10/ 13/ 18/ 1 Pulse duration, AECLKOUT2 high tw(
48、EKO2H)0.5NE-0.7 0.5NE+0.7 2 Pulse duration, AECLKOUT2 low tw(EKO2L)0.5NE-0.7 0.5NE+3 Transition time, AECLKOUT2 tt(EKO2)1 4 Delay time, AECLKIN high to AECLKOUT2 high td(EKIH-EKO2H)1 8 5 Delay time, AECLKIN low to AECLKOUT2 low td(EKIL-EKO2L)See figure 15 1 8 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-
