DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf

上传人:tireattitude366 文档编号:689257 上传时间:2018-12-30 格式:PDF 页数:24 大小:220.31KB
下载 相关 举报
DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf_第1页
第1页 / 共24页
DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf_第2页
第2页 / 共24页
DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf_第3页
第3页 / 共24页
DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf_第4页
第4页 / 共24页
DLA DSCC-VID-V62 08622-2009 MICROCIRCUIT DIGITAL-LINEAR 12 BIT SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE MONOLITHIC SILICON.pdf_第5页
第5页 / 共24页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 24 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RAJESH PITHADIA DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-

2、3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, SERIAL, ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE, MONOLITHIC SILICON 09-07-29 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08622 REV PAGE 1 OF 24 AMSC N/

3、A 5962-V070-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a 12-bit, se

4、rial, analog-to-digital converter with internal reference, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identi

5、fying the item on the engineering documentation: V62/08622 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TLV2556-EP 12-bit, serial, analog-to-digital converter with internal reference 1.2

6、.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Ma

7、terial A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 3 1

8、.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V to 6.5 V Input voltage range (VIN) (any input) -0.3 V to VCC+ 0.3 V Output voltage range (VOUT) . -0.3 V to VCC+ 0.3 V Positive reference voltage range ( VREF+) . -0.3 V to VCC+ 0.3 V Negative reference voltage range (VREF-) . -0.3

9、 V to VCC+ 0.3 V Peak input current (II) (any input) . 20 mA Peak total input current (all inputs) . 30 mA Operating virtual junction temperature range (TJ) -55C to 150C Operating free-air temperature range (TA) . -55C to 125C Storage temperature range (TSTG) . -65C to 150C Lead temperature (1.6 mm,

10、 at distance 1/16 inch from case for 10 seconds) 260C 1.4 Recommended operating conditions. 3/ Supply voltage (VCC) 2.7 V min to 5.5 V max SCLK frequency: VCC= 4.5 V to 5.5 V, 16 bit I/O 0.01 MHz min to 15 MHz max VCC= 4.5 V to 5.5 V, 12 bit I/O 0.01 MHz min to 15 MHz max VCC= 4.5 V to 5.5 V, 8 bit

11、I/O 0.01 MHz min to 15 MHz max VCC= 2.7 V to 3.6 V 0.01 MHz min to 10 MHz max Tolerable clock jitter, I/O CLOCK, VCC= 4.5 V to 5.5 V 0.38 ns max Aperature jitter, VCC= 4.5 V to 5.5 V 100 ps nominal Analog input voltage : 4/ VCC= 4.5 V to 5.5 V 0 V min to (REF+) (REF-) V max VCC= 3 V to 3.6 V . 0 V m

12、in to (REF+) (REF-) V max VCC= 2.7 V to 3 V . 0 V min to (REF+) (REF-) V max High level control input voltage (VIH): VCC= 4.5 V to 5.5 V 2 V min VCC= 2.7 V to 3.6 V 2.1 V min Low level control input voltage (VIH): VCC= 4.5 V to 5.5 V 0.8 V max VCC= 2.7 V to 3.6 V 0.6 V max Operating free-air tempera

13、ture range (TA) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition

14、s” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Unless otherwise specified, all voltage values are with respect to the GND terminal with REF- and GND wired together. 3/ Use of this product beyond the manufacturers design rules o

15、r stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than t

16、he voltage applied to REF- convert as all zeros (000000000000). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB

17、95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly mark

18、ed with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable

19、) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified

20、herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproductio

21、n or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max High level outp

22、ut voltage VOHVCC= 4.5 V, IOH= -1.6 mA VCC= 2.7 V, IOH= -0.2 mA 30 pF -55C to +125C 01 2.4 V VCC= 4.5 V, IOH= -20 A VCC= 2.7 V, IOH= -20 A 30 pF VCC 0.1 Low level output voltage VOLVCC= 5.5 V, IOL= 1.6 mA VCC= 3.6 V, IOL= 0.8 mA 30 pF -55C to +125C 01 0.4 V VCC=5.5 V, IOL= -20 A VCC= 3.6 V, IOL= -20

23、 A 30 pF 0.1 High impedance off state output current IOZVOUT= VCC, = VCC-55C to +125C 01 2.5 A VOUT= 0 V, = VCC-2.5 Operating supply current ICCat 0 V, external reference, VCC= 5 V -55C to +125C 01 1.2 mA at 0 V, external reference, VCC= 2.7 V 0.9 at 0 V, internal reference, VCC= 5 V 3 at 0 V, inter

24、nal reference, VCC= 2.7 V 2.4 Software power down current ICC(SPD)For all digital inputs, 0 V VIN 0.5 V or VIN VCC 0.5 V, SCLK = 0 V, external reference -55C to +125C 01 10 A For all digital inputs, 0 V VIN 0.5 V or VIN VCC 0.5 V, SCLK = 0 V, internal reference 10 See footnotes at end of table. Prov

25、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Temperature,

26、 TA Device type Limits Unit Min Max Auto power down current ICC(APD)For all digital inputs, 0 V VIN 0.5 V or VIN VCC 0.5 V, SCLK = 0 V, external reference -55C to +125C 01 10 A For all digital inputs, 0 V VIN 0.5 V or VIN VCC 0.5 V, SCLK = 0 V, internal reference 1800 High level input current IIHVIN

27、= VCC-55C to +125C 01 2.5 A Low level input current IILVIN = 0 V -55C to +125C 01 -2.5 A Selected channel leakage current IIKGSelected channel at VCC, Unselected channel at 0 V -55C to +125C 01 1 A Selected channel at 0 V, Unselected channel at VCC-1 Internal oscillator frequency f(OSC)VCC= 4.5 V to

28、 5.5 V -55C to +125C 01 3.0 MHz VCC= 2.7 V to 3.6 V 2.1 Conversion time = 13.5 x f(OSC)+ 25 ns tconvVCC= 4.5 V to 5.5 V -55C to +125C 01 4.53 s VCC= 2.7 V to 3.6 V 6.46 Internal oscillator frequency switch-over voltage +25C 01 3.9 typical V Analog input MUX impedance 3/ ZiVCC= 4.5 V +25C 01 600 typi

29、cal VCC= 2.7 V 500 typical Input capacitance CINAnalog inputs +25C 01 45 typical pF Control inputs 5 typical See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDE

30、NT NO. 16236 DWG NO. V62/08622 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max External reference section 4/ Reference input voltage REF- VCC = 4.5 V to 5.5 V -55C to +125C 01 -0.1 0.1 V VCC= 2.7 V t

31、o 3.6 V -0.1 0.1 Reference input voltage REF+ VCC = 4.5 V to 5.5 V -55C to +125C 01 2 VCCV VCC= 2.7 V to 3.6 V 2 VCCExternal reference input voltage difference (REF+) (REF-) VCC = 4.5 V to 5.5 V -55C to +125C 01 1.9 VCCV VCC= 2.7 V to 3.6 V 1.9 VCCExternal reference supply current = 0 V, VCC = 4.5 V

32、 to 5.5 V -55C to +125C 01 1 mA = 0 V, VCC = 2.7 V to 3.6 V 0.7 Reference input impedance VCC = 5 V, static +25C 01 1 typical M VCC = 5 V, during sampling/conversion 9 typical k VCC = 2.7 V, static 1 typical M VCC = 2.7 V, during sampling/conversion 9 typical k Internal reference section 5/ Referenc

33、e input voltage REF- VCC = 2.7 V to 5.5 V, REF- = Analog GND +25C 01 0 typical V Internal reference voltage difference (REF+) (REF-) VCC= 5.5 V, Internal 4.096-V VREF selected -55C to +125C 01 3.95 4.25 V VCC= 5.5 V, Internal 2.048-V VREF selected 1.94 2.15 VCC= 2.7 V, Internal 2.048-V VREF selected

34、 1.94 2.15 Internal reference start up time VCC= 5 V, with 10 F load +25C 01 20 typical ms VCC= 2.7 V, with 10 F load 20 typical Internal reference temperature coefficient VCC= 2.7 V to 5.5 V +25C 01 50 typical ppm/C See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or netw

35、orking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max Integral non

36、linearity error 6/ INL -55C to +125C 01 -1 1 LSB Differential nonlinearity error DNL -55C to +125C 01 -1 1 LSB Offset error 7/ 8/ EO-55C to +125C 01 -2 2 mV Gain error 7/ 8/ EG-55C to +125C 01 -3 3 mV Total unadjusted error 9/ ET+25C 01 1.5 typical LSB Self test output code 10/ Address data input =

37、1011 +25C 01 2048 typical Address data input = 1100 0 typical Address data input = 1101 4095 typical Pulse duration I/O CLOCK high or low 11/ tw112/ -40C to +85C 01 26.7 100000 ns Setup time DATA IN valid before I/O CLOCK rising edge 11/ tsu1See figure 4 12/ -40C to +85C 01 12 ns Hold time DATA IN v

38、alid after I/O CLOCK risign edge 11/ th1See figure 4 12/ -40C to +85C 01 0 ns Setup time low before 1strising I/O CLOCK edge 11/ 13/ tsu2See figure 5 12/ -40C to +85C 01 25 ns Hold time pulse duration high time 11/ th2See figure 5 12/ -40C to +85C 01 100 ns Hold time low after last I/O CLOCK falling

39、 edge 11/ th3See figure 5 12/ -40C to +85C 01 0 ns Hold time DATA OUT valid after I/O CLOCK falling edge 11/ th4See figure 6 12/ -40C to +85C 01 2 ns Hold time high after EOC rising edge when is toggled 11/ th5See figure 7 12/ -40C to +85C 01 0 ns Hold time high after falling edge 11/ th6See figure

40、7 12/ -40C to +85C 01 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 9 TABLE I. Electrical performance characte

41、ristics - Continued. 1/ Test Symbol Conditions 12/ Temperature, TA Device type Limits Unit Min Max Hold time I/O CLOCK low after EOC rising edge or falling edge when is held low 11/ th7See figure 8 -40C to +85C 01 10 ns Delay time falling edge to DATA OUT valid (MSB or LSB) 11/ td1Load = 25 pF, See

42、figure 9 -40C to +85C 01 28 ns Load = 10 pF, See figure 9 -40C to +85C 01 20 Delay time rising edge to DATA OUT high impedance 11/ td2See figure 9 -40C to +85C 01 10 ns Delay time I/O CLOCK falling edge to next DATA OUT bit valid 11/ td3See figure 6 -40C to +85C 01 2 20 ns Delay time last I/O CLOCK

43、falling edge to EOC falling edge 11/ td4See figure 10 -40C to +85C 01 55 ns Delay time last I/O CLOCK falling edge to falling edge to abort conversion 11/ td5-40C to +85C 01 1.5 s Delay time last I/O CLOCK falling edge to falling edge 11/ td6See figure 10 -40C to +85C 01 MAX(tconv) ns Delay time EOC

44、 rising edge or falling edge to DATA OUT valid: MSB or LSB first 11/ td7See figure 11 -40C to +85C 01 4 ns Delay time I/O CLOCK high to rising edge when is held low 11/ td9See figure 8 -40C to +85C 01 1 28 ns Transition time I/O CLOCK 11/ 13/ tt1See figure 6 -40C to +85C 01 1 s See footnotes at end

45、of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08622 REV PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions

46、12/ Temperature, TA Device type Limits Unit Min Max Transition time DATA OUT 11/ tt2See figure 6 -40C to +85C 01 5 ns Transition time /EOC, CL= 7 pF 11/ tt3See figures 10 and 11 -40C to +85C 01 2.4 ns Transition time DATA IN, 11/ tt4-40C to +85C 01 10 s Total cycle time (sample, conversion and delay

47、s) 11/ 13/ tcyc-40C to +85C 01 MAX(tconv) + I/O period (8/12/16 CLKs) s Channel acquisition time (sample), at 1 k 11/ 13/ tsampleSource impedance = 25 -40C to +85C 01 600 ns Source impedance = 100 01 650 Source impedance = 500 01 700 Source impedance = 1 k 01 1000 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1