1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct the maximum operating temperature range in section 1.1, 1.3 and 1.4. - phn 09-08-18 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREP
2、ARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE DRIVER WITH 15 kV ESD PROTECTION, MONOLITHIC SILICON 08-12-10 APPROVED BY Thomas M
3、. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09603 REV A PAGE 1 OF 11 AMSC N/A 5962-V078-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV A PAGE 2 1
4、. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage high speed quadruple differential line driver with 15 kV ESD protection microcircuit, with an operating temperature range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The
5、manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09603 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device typ
6、e(s). Device type Generic Circuit function 01 AM26LV31E-EP Low voltage high speed quadruple differential line driver with 15 kV ESD protection 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small outlin
7、e package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or n
8、etworking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +6.0 V 2/ Input voltage range (VI) . -0.5 V to + 6.0 V Output voltage ran
9、ge (VO) . -0.5 V to +6.0 V Input clamp current (IIK) (VI 0) . -20 mA Output clamp current (IOK) (VO 0) . -20 mA Continuous output current (IO) . 150 mA Continuous current through VCC or GND . 200 mA Package thermal impedance (JA) . 73C/W 3/ 4/ Operating virtual junction temperature range (TJ) +150C
10、Storage temperature range -65C to +150C Operating free-air temperature range (TA) . -55C to +105C 1.4 Recommended operating conditions. Supply voltage range (VCC) . 3.0 V to 3.6 V Input voltage (VI) 0 V to 5.5 V Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL) . 0.8
11、 V Maximum high level output current (IOH) . -30 mA Maximum low level output current (IOL) . +30 mA Operating free-air temperature range (TA) . -55C to +105C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and f
12、unctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values, except differential input voltag
13、e are with respect to network GND. 3/ Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD= (TJ(max) TA) / JA. Selecting the maximum of +150C can affect reliability. 4/ The package thermal impedance is calc
14、ulated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 4 2. APPLICABLE DOCUMENTS ELECTRONICS INDUSTRIES ALLIANCE (EIA)
15、 JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices. JESD 51-7 High effective-thermal-conductivity test board for leaded surface- mount packages. TIA/EIA-422-B Electrical Characteristics of Balanced Voltage Digital Interface Circuits. (Applications for copies should be addressed
16、 to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org or http:/www.eia.org) INTERNATIONAL ELECTROTECHNICAL COMMISSION (IEC) IEC 61000-4-2 Electromagnetic compatibility (EMC) Part 4-2: Testing and measurement techniques Electrostatic
17、discharge immunity test. (Applications for copies should be addressed to the IEC Central Office, 3 Rue de Varembe, P.O. Box 131, CH 1211 GENEVA 20, Switzerland or online at http:/www.iec.ch). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part numbe
18、r as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characterist
19、ics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case out
20、line. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The function table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Test
21、 circuits. The test circuits shall be as shown in figures 5. 3.5.6 Timing waveforms. The timing waveforms shall be as shown in figures 6-8. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDE
22、NT NO. 16236 DWG NO. V62/09603 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max High level output voltage VOHVIH= 2 V, VIL= 0.8 V, IOH= -20 mA 2.4 V Low level output voltage VOLVIH= 2 V, VIL= 0.8 V, IOL= 20 mA 0.4 Differential output voltag
23、e |VOD1| IO= 0 mA 2 4 Differential output voltage |VOD2| RL= 100 , See figure 5 3/ 2 Change in magnitude of differential output voltage |VOD| RL= 100 , See figure 5 3/ 0.4 Common mode output voltage VOCRL= 100 , See figure 5 3/ 1.5 2 Change in magnitude of common mode output voltage |VOC| RL= 100 ,
24、See figure 5 3/ 0.4 Output current with power off IO(OFF)VCC= 0, VO= -0.25 V or 5.5 V 127 A High impedance state output current IOZVO= -0.25 V or 5.5 V, G = 0.8 V or G = 2 V 127 Input current II VCC= 0 or 3.6 V, VI=0 or 5.5 V 10 Short circuit output current IOSVO= VCCor GND 4/ -30 -150 mA Supply cur
25、rent (total package) ICCVI= VCCor GND, No load, enable 100 A Power dissipation capacitance CpdNo load, VCC= 3.3 V, TA = 25C 5/ 160 TYP pF Switching characteristics Propagation delay time, high to low level output tPHLSee figure 6 4 12 ns Propagation delay time, low to high level output tPLH3.5 12 Tr
26、ansition time (tr or tf) ttSee figure 6 10 Output enable time to high level tPZHSee figure 7 20 Output enable time to low level tPZLSee figure 8 20 Output disable time from high level tPHZSee figure 7 20 Output disable time from low level tPLZSee figure 8 20 Pulse skew tsk(p)See figure 6 6/ 7/ 3 Ske
27、w limit (pin to pin) tsk(o)1.5 Skew limit (device to device) tsk(lim)3 Maximum operating frequency fmaxSee figure 6 32 TYP MHz ESD protection Driver output HBM 15 kV IEC6100-4-2, Air gap discharge 15 IEC6100-4-2, Constant discharge 8 1/ Testing and other quality control techniques are used to the ex
28、tent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by charact
29、erization and/or design. 2/ Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted). 3/ Refer to TIA-EIA-422 for exact conditions. 4/ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second
30、. 5/ Cpddetermined the no load dynamic current consumption: IS= Cpdx VCC x f + ICC6/ Pulse skew is defined as the |tPLH tPHL| of each channel of the same device. 7/ Skew limit (device to device) is the maximum difference in propagation delay times between any two channels of any two devices. Provide
31、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 6 Case X Symbols Inches Millimeters Symbols Inches Millimeters Min Max Min Max Min Max Min Max A - 0.069 -
32、1.75 E 0.150 0.157 3.80 4.00 A1 0.004 0.010 0.10 0.25 E1 0.228 0.244 5.80 6.20 b 0.012 0.020 0.31 0.51 e 0.050 BSC 1.27 BSC c 0.007 0.010 0.17 0.25 L 0.016 0.050 0.40 1.27 D 0.386 0.394 9.80 10.00 NOTES: 1. All linear dimensions are in inches (millimeters). 2. Body length does not include mold flash
33、, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch (0.15 mm) per end. 3. Body width does not include interlead flash. Interlead flash shall not exceed .017 inch (0.43 mm) per side. 4. Falls within JEDEC MS-012 variation AC. FIGURE 1. Case outlines - Conti
34、nued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 7 Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 9 3A 2 1Y 10 3Y 3 1Z 11
35、 3Z 4 G 12 G 5 2Z 13 4Z 6 2Y 14 4Y 7 2A 15 4A 8 GND 16 VCCFIGURE 2. Terminal connections. Input A Enables Outputs G G Y Z H H X H L L H X L H H X L H L L X L L H X L H Z Z FIGURE 3. Function table. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without
36、license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 8 FIGURE 5. Test circuit, VODand VOC. NOTES: 1. CL include probe and jig capacitance. 2. The input pulse is supplied by generators having the following characteristics: PRR 32 M
37、Hz, 50 % duty cycle, trand tf 2 ns. FIGURE 6. Timing waveforms, tPHLand tPLH. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 9 NOTES: 1. CL include
38、 probe and jig capacitance. 2. The input pulse is supplied by generators having the following characteristics: PRR = 10 MHz, 50 % duty cycle, tr= tf 2 ns. 3. To test the active low enable G , ground G and apply an inverted waveform G . FIGURE 7. Timing waveforms, tPZHand tPHZ. Provided by IHSNot for
39、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 10 NOTES: 1. CL include probe and jig capacitance. 2. The input pulse is supplied by generators having the following chara
40、cteristics: PRR = 10 MHz, 50 % duty cycle, tr= tf 2 ns. 3. To test the active low enable G , ground G and apply an inverted waveform G . FIGURE 8. Timing waveforms, tPZLand tPLZ. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,
41、COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09603 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include prope
42、r handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices f
43、or electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device ma
44、nufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of
45、 supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/09603-01XE 01295 AM26LV31ESDREP A26LV31ESP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineer
46、ing documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturers datasheet, or at website . CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Ln. PO Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
