1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H
2、. Nguyen APPROVED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, BiCMOS POWER FACTOR PREREGULATOR, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09617 YY MM DD 09-01-27 REV PAGE 1 OF 9 AMSC N/A 5962-V025-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without
3、 license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance BiCMOS power factor preregulator microcircuit, with an operating temperature range o
4、f -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09617 - 01 X E Drawing Device type Case out
5、line Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Turn On Threshold Generic Circuit function 01 10.2 V UCC2818-EP BiCMOS power factor preregulator. 02 UCC2817-EP BiCMOS power factor preregulator. 1.2.2 Case outline(s). The case outlines are as specified he
6、rein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MS-012 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Go
7、ld plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Maximum suppl
8、y voltage, (VCC) +18.0 V Maximum supply current, (ICC) . 20 mA Maximum gate drive current, continuous 0.2 A Maximum gate drive current . 1.2 A Maximum input voltage, (VI): CAI, MOUT, SS . +8.0 v PKLMT +5.0 V VSENSE, OVP/EN +10.0 V Maximum input current: RT, IAC, PKLMT . 10 mA VCC(no switching) . 20
9、mA Maximum negative voltage (DRVOUT, PKLMT, MOUT) -0.5 V Maximum power dissipation . 1 W Junction temperature, (TJ) -55C to +150C Storage temperature range, (TSTG) -65C to +150C Lead temperature, (Tsol), (Soldering, 10 s) 300C Package thermal impedance: (JA) Package JC(C/W) JA(C/W) Case outline X 22
10、 40 to 70 2/ 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 1/ Stresses beyond those listed un
11、der “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions
12、 for extended periods may affect device reliability. 2/ Specified JA(junction to ambient) is for device mounted to 5 in2FR4 PC board with 1 oz cooper, where noted. When resistance range is given, lower values are for 5 in2aluminum PC board. Test PWB was 0.062 in thick and typically used 0.625 mm tra
13、ce widths for power packages and 1.33 mm trace widths for nonpower packages with a 100 mil x 100 mil probe land area at the end of each trace. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE
14、IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit c
15、ontainer. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein.
16、3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in fig
17、ure 2. 3.5.3 Block diagram. The lblock diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 5 TABLE I. Electrical
18、performance characteristics. 1/ Limits Test Conditions 2/ unless otherwise specified Device type Min Max Unit Supply current Supply current, off VCC= (VCCturn-on threshold 0.3 V) 300 A Supply current, on VCC= 12 V, No load on DRVOUT All 2 6 mA UVLO VCCturn-on threshold 02 15.4 16.6 VCCturn-off thres
19、hold 02 9.4 UVLO hysteresis 02 5.8 Maximum shunt voltage 02 15.4 17.5 VCCturn-on threshold 01 9.7 10.9 VCCturn-off threshold 01 9.4 UVLO hysteresis 01 0.3 V Voltage amplifier Input voltage 7.309 7.691 V VSENSEbias current VSENSE= VREF, VAOUT = 2.5 V 200 nA Open loop gain VAOUT = 2 V to 5 V 50 dB Hig
20、h level output voltage IL= -150 A 5.3 5.6 V Low level output voltage IL= 150 A All 0 150 mV Overvoltage Protection and Enable Overvoltage reference VREF + 0.48 VREF + 0.52 V Hysteresis 300 600 mV Enable Threshold 1.7 2.1 V Enable hysteresis All 0.1 0.3 V Current Amplifier Input offset voltage VCM= 0
21、 V, VCAOUT= 3 V -3.5 2.5 mV Input bias current VCM= 0 V, VCAOUT= 3 V -100 nA Input offset current VCM= 0 V, VCAOUT= 3 V 100 nA Open loop gain VCM= 0 V, VCAOUT= 2 V to 5 V 86 dB Common mode rejection ratio VCM= 0 V to 1.5 V, VCAOUT= 3 V 55 dB High level output voltage IL= -120 mA 5.6 6.9 V Low level
22、output voltage IL= 1 mA 0.1 0.5 V Gain bandwidth product 3/ All 2.5 TYP MHz Voltage reference Input voltage 7.3 7.65 V Load regulation IREF= 1 mA to 2 mA 0 10 mV Line regulation VCC= 10.8 V to 15 V 0 10 mV Short circuit current VREF= 0 V All -20 -50 mA See footnote at end of the table. Provided by I
23、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. Limits Test Conditions 2/ unless otherwise specified
24、 Device type Min Max Unit Oscillator Initial accuracy TA= 25C 85 115 kHz Voltage stability VCC= 10.8 V to 15 V -1.5% 1.5% Total variation Line, temperature 80 120 kHz Ramp peak voltage 4.5 5.5 V Ramp amplitude voltage (peak to peak) All 3.5 4.5 V Peak current limit PKLMT reference voltage -15 15 mV
25、PKLMT propagation delay All 150 500 ns Multiplier High line, low power output current IAC= 500 A, VFF= 4.7 V, VAOUT= 1.25 V 11 -33 High line, high power output current IAC= 500 A, VFF= 4.7 V, VAOUT= 5 V -53 -112 Low line, low power output current IAC= 150 A, VFF= 1.4 V, VAOUT= 1.25 V -8 -50 Low line
26、, high power output current IAC= 150 A, VFF= 1.4 V, VAOUT= 5 V -268 -350 IAC limited output current IMOUTIAC= 150 A, VFF= 1.3 V, VAOUT= 5 V -250 -400 A Gain constant (K) IAC= 20 A, VFF= 3V, VAOUT= 2.5 V 0.5 1/V IAC= 150 A, VFF= 1.4 V, VAOUT= 0.25 V -2 IAC= 500 A, VFF= 4.7 V, VAOUT= 0.25 V -2 Zero cu
27、rrent IMOUTIAC= 500 A, VFF= 4.7 V, VAOUT= 0.5 V -3.5 A Power limit (IMOUTx VFF) All -375 W Feed Forward VFF output current IAC= 300 A, All -140 -160 A Soft Start Softstart charge current All -6 -16 A Gate Driver Pullup resistance IO= -100 mA to -200 mA 12 Pulldown resistance IO= -100 mA 10 Output ri
28、se time CL= 1 nF, RL= 10 , VDRVOUT= 0.7 V to 9 V 50 Output fall time CL= 1 nF, RL= 10 , VDRVOUT= 9 V to 0.7 V 50 ns Maximum duty cycle 93% 99% Maximum controlled duty cycle At 100 kHz All 2% Zero Power Zero power comparator threshold Measured on VAOUT All 0.2 0.5 V 1. Testing and other quality contr
29、ol techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product p
30、erformance is assured by characterization and/or design. 2. TA= -55C to +125C, TA= TJ, VCC= 12 V, RT= 22 k, CT= 270 pF (unless otherwise noted). 3. Ensured by design, not production tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPP
31、LY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 7 Case X Dimensions Symbol Min Max Symbol Min Max A 1.75 e 1.27 BSC A1 0.10 0.25 E 3.80 4.00 b 0.31 0.51 E1 5.80 6.20 c 0.13 0.25 L 0.40 1.27 D 9.80 10.00 Notes: 1. All linear dimensions are in millimeters. 2.
32、This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, or gate burrs. Mold flash or protrusion, or gate burrs shall not exceed 0.15 mm per end. 4. Body width does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side 5.
33、Reference JEDEC MS-012 variation AC. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 8 Pin No. Signal name Pin No. Signal n
34、ame 1 GND 9 VREF 2 PKLMT 10 OVP/EN 3 CAOUT 11 VSENSE 4 CAI 12 RT 5 MOUT 13 SS 6 IAC 14 CT 7 VAOUT 15 VCC 8 VFF 16 DRVOUT FIGURE 2. Terminal connections. FIGURE 3. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C
35、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09617 REV PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper
36、handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for
37、 electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manu
38、facturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of s
39、upply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/09617-01XE 01295 UCC2818MDREP V62/09617-02XE 2/ UCC2817MDREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineeri
40、ng documentation. 2/ Not available from an approved source of supply. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
