1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY Phu H. Ng
2、uyen TITLE MICROCIRCUIT, DIGITAL, SINGLE 3-INPUT POSITIVE AND GATE, MONOLITHIC SILICON 10-01-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09621 REV PAGE 1 OF 9 AMSC N/A 5962-V027-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
3、HS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single 3-input positive AND gate microcircuit, with an operating temperature range of -55C to +125C
4、. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09621 - 01 X E Drawing Device type Case outline Lead finis
5、h number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC1G11-EP Single 3-input positive AND gate 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 6 MO-203 Plastic sma
6、ll outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage rang
7、e ( VCC) . -0.5 V to 6.5 V Input voltage range ( VI) -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high impedance or power off state ( VO) -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high or low state ( VO) -0.5 V to VCC+0.5 V 2/ 3/ Maximum input clamp current ( IIK
8、) ( VI 0 ) . -50 mA Maximum output clamp current ( IOK) ( VO 0 ) -50 mA Maximum continuous output current ( IO) 50 mA Maximum continuous current through VCCor GND 100 mA Maximum package thermal impedance ( JA) 259C/W 4/ Storage temperature range (TSTG) -65C to 150C 1/ Stresses beyond those listed un
9、der “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated condition
10、s for extended periods may affect device reliability. 2/ The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ This value of VCCis provided in the recommended operating conditions stable. 4/ The package thermal impedance is cal
11、culated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 3 1.4 Recommended operating conditions. 5/ 6/ Supply voltage r
12、ange ( VCC): Operating 1.65 V to 5.5 V Minimum data retention only . 1.5 V Minimum high level input voltage VCC= 1.65 V to 1.95 V . 0.65 x VCCVCC= 2.3 V to 2.7 V . 1.7 V VCC= 3 V to 3.6 V 2.0 V VCC= 4.5 V to 5.5 V . 0.7 x VCCMaximum high level input voltage VCC= 1.65 V to 1.95 V . 0.35 x VCCVCC= 2.3
13、 V to 2.7 V . 0.7 V VCC= 3 V to 3.6 V 0.8 V VCC= 4.5 V to 5.5 V . 0.3 x VCCInput voltage ( VI) . 0 V to 5.5 V Output voltage (VO) 0 to VCCMaximum high level output current ( IOH): VCC= 1.65 V . -4 mA VCC= 2.3 V . -8 mA VCC= 3 V -16 mA VCC= 3 V -24 mA VCC= 4.5 V . -32 mA Maximum low level output curr
14、ent ( IOL): VCC= 1.65 V . 4 mA VCC= 2.3 V . 8 mA VCC= 3 V 16 mA VCC= 3 V 24 mA VCC= 4.5 V . 32 mA Maximum input transition rise or fall rate (t/v) : VCC= 1.8 V 0.15 V, 2.5 V 0.2 V 20 ns/V VCC= 3.3 V 0.3 V . 10 ns/V VCC= 5.0 V 0.5 V . 10 ns/V Operating free-air temperature range ( TA) -55C to +125C 2
15、. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Ar
16、lington, VA 22201-3834 or online at http:/www.jedec.org) _ 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor
17、maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 4 3. REQUIREMENTS
18、 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufa
19、cturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design
20、, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The function table shall be as shown
21、in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Load circuit and timing waveforms. The load circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE S
22、UPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -55C TA 125C unless otherwise specified VCCLimits Unit Min Max High level output voltage VOHIOH= -100 A 1.65 V to 5.5 V VCC 0.1 V
23、IOH= -4 mA 1.65V 1.2IOH= -8 mA 2.3 V 1.9 IOH= -16 mA 3.0 V 2.4 IOH= -24 mA 2.3 IOH= -32 mA 4.5 V 3.8 Low level output voltage VOLIOL= 100 A 1.65 V to 5.5 V 0.1 V IOL= 4 mA 1.65V 0.45IOL= 8 mA 2.3 V 0.3 IOL= 16 mA 3.0 V 0.4 IOL= 24 mA 0.55IOL= 32 mA 4.5 V 0.55 Input current All inputs IIVI= 5.5 V or
24、GND 0 to 5.5 V 5 A Off current IoffVIor VO= 5.5 V 0 10 A Supply current ICCVI= 5.5 V or GND, IO= 0, 1.65 V to 5.5V 10 A Quiescent supply current ICCOne input at VCC 0.6 V, Other input at VCCor GND 3.0 V to 5.5V 500 A Input capacitance CiVI= VCCor GND, TA= 25C 3.3 V 3.5 TYP pF Test Symbol Conditions
25、-55C TA 125C unless otherwise specified VCC= 1.8 V 0.15 V VCC= 2.5 V 0.3 V VCC= 3.3 V 0.3 V VCC= 5.0 V 0.5 V Unit Min Max Min Max Min Max Min Max Switching characteristics Propagation delay time, from input A , B or C to output Y tpdSee figure 5 2.9 17.2 1.4 7.5 1.3 5.9 1 5.0 ns Operating characteri
26、stics Power dissipation capacitance Cpdf = 10 MHz, TA= 25C 18 TYP 19 TYP 20 TYP 23 TYP pF 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full
27、temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER
28、, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 6 Case X Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.80 1.10 E 1.10 1.40 A1 0.00 0.10 E1 1.80 2.40 b 0.15 0.30 e 0.65 BSC c 0.08 0.22 L 0.26 0.46 D 1.85 2.15 L1 0.15 NOM NOTES: 1. This drawing is
29、 subject to change without notice. 2. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 mm per side. 3. Falls within JEDEC MO-203 variation AB. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without
30、license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 7 Case X Terminal number Terminal symbol Terminal number Terminal symbol 1 A 4 Y 2 GND 5 VCC3 B 6 C FIGURE 2. Terminal connections. Inputs Output Y A B c H H H H L X X L X L X L
31、 X X L L FIGURE 3. Function table. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 8 NOTES: 1. CLincludes probe and jig cap
32、acitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by
33、generators having the following characteristics: PRR 10 MHz, ZO= 50 . 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPHLand tPLHare the same as tpd. 8. All parameters and waveforms are
34、not applicable to all devices. FIGURE 5. Load circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09621 REV PAGE 9 4. VERIFICATION 4.1 Pr
35、oduct assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensi
36、tive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sen
37、sitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes a
38、re provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code
39、 Vendor part number Top side Marking V62/09621-01XE 01295 SN74LVC1G11DCKREP OBF 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
