1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add footnote to paragraphs 1.2.2 and 6.3. Make changes to figure 1 and the dimensions table. - ro 12-01-12 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with AS
2、ME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA MICROCIRCUIT, DIGITAL-LIN
3、EAR, HIGH OUTPUT CURRENT PULSE WIDTH MODULATION CONVERTER, MONOLITHIC SILICON 09-04-14 APPROVED BY JOSEPH D. RODENBECK SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09625 REV A PAGE 1 OF 11 AMSC N/A 5962-V017-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS
4、-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance high output current pulse width modulation converter microcircuit, with an operating temperature ra
5、nge of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09625 - 01 X E Drawing Device type Cas
6、e outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS5430-EP High output current pulse width modulation converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 9
7、5 Package style X 1/ 8 MS-012-BA Plastic surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other _ 1/
8、 The manufacture has changed lead frames NiPdAu to NiPdAuAg and location of assembly from their Hana facility to their Shanghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a NiPdAu frame from the Hana facility. Provided by IHSNot for ResaleNo reproduction or networking permitte
9、d without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 3 1.3 Absolute maximum ratings. 2/ 3/ Input voltage range (VIN): VINpin -0.3 V to 40 V 4/ BOOT pin . -0.3 V to 50 V PH pin (steady state) -0.6 V to 40 V 4/ ENA pin -
10、0.3 V to 7 V BOOT-PH pin . 10 V VSENSE pin . -0.3 V to 3 V PH pin (transient 10 ns) -1.2 V Source current (IO) (PH pin) . Internally limited Leakage current (IILK) (PH pin) 10 A Operating virtual junction temperature range . -55C to +150C Storage temperature range -65C to +150C 1.4 Recommended opera
11、ting conditions. 5/ Input voltage range (VIN) . 5.5 V to 36 V Operating junction temperature range (TJ) -55C to +125C 1.5 Dissipation ratings table. 6/ 7/ Package Thermal impedance junction to ambient 2 layer board with solder 8/ 33C/W 4 layer board with solder 9/ 26C/W 2/ Stresses beyond those list
12、ed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated condi
13、tions for extended periods may affect device reliability. 3/ All voltages are within respect to device GND terminal. 4/ Approaching the absolute maximum rating for the VINpin may cause the voltage on the PH pin to exceed the absolute maximum rating. 5/ Use of this product beyond the manufacturers de
14、sign rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ Maximum power dissipation may be limited by overcurrent protection. 7/ Power rating at a specific ambient temperature T
15、Ashould be determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final printed circuit board (PCB) should strive to keep the junction temperature at or below 125C for performance and long term reliability. 8/ Te
16、st board conditions: 3 inch x 3 inch, two layers, thickness: 0.062 inch. 2 ounce copper traces located on the top and bottom of the PCB. Six thermal vias in the thermal pad area under the device package. 9/ Test board conditions: 3 inch x 3 inch, four layers, thickness: 0.062 inch. 2 ounce copper tr
17、aces located on the top and bottom of the PCB. 2 ounce copper ground planes on the two internal layers. Six thermal vias in the thermal pad area under the device package. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS
18、 COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street
19、, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identif
20、ication (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1
21、.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections s
22、hall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAG
23、E 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VIN= 12 V unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Supply voltage (VINpin) section Quiescent current IQVSENSE = 2 V, not switching, PH pin open -55C to +125C 01 4.4 mA Shutdown, ENA = 0 V 5
24、0 A Undervoltage lockout (UVLO) section Start threshold voltage VTH-55C to +125C 01 5.3 typical V Hysteresis voltage VHYS-55C to +125C 01 330 typical mV Voltage reference section Voltage reference accuracy VRAIO= 0 A to 3 A 25C 01 1.202 1.239 V -55C to +125C 1.196 1.245 Oscillator section Internally
25、 set free running frequency fISFR-55C to +125C 01 400 600 kHz Minimum controllable on time tcmin-55C to +125C 01 200 ns Maximum duty cycle DCMAX-55C to +125C 01 87 % Enable (ENA pin) section Start threshold voltage VSTART-55C to +125C 01 1.3 V Stop threshold voltage VSTOP-55C to +125C 01 0.5 V Hyste
26、resis voltage VHYS-55C to +125C 01 450 typical mV Internal slow start time tISS(0 100%) -55C to +125C 01 5.4 10 ms Current limit section Current limit IL-55C to +125C 01 4 8.5 A Current limit hiccup time tCL-55C to +125C 01 13 21 ms See footnotes at end of table. Provided by IHSNot for ResaleNo repr
27、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VIN= 12 V unless otherwise specifiedTemperature
28、, TJDevice type Limits Unit Min Max Thermal shutdown section Thermal shutdown trip point TTSTP-55C to +125C 01 135 C Thermal shutdown hysteresis TTSH-55C to +125C 01 14 typical C Output MOSFET section High side power MOSFET switch rDS(on)VIN= 5.5 V -55C to +125C 01 150 typical m 230 1/ Testing and o
29、ther quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric
30、testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 7 Case X FIGURE 1. Case
31、 outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 8 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A1 0.00 0.005 0
32、.00 0.15 A2 - 0.066 - 1.70 b 0.012 0.020 0.31 0.51 c 0.007 nominal 0.20 nominal D 0.188 0.196 4.80 5.00 E 0.149 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 e 0.05 BSC 1.27 BSC L 0.015 0.05 0.40 1.27 n 8 8 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2.
33、Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.005 inch). 3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package, manufacturers literature number SLMA002 for information regarding reco
34、mmended board layout. A copy of the datasheet is available from the manufacturer. 4. Falls within reference to JEDEC MS-012-BA. FIGURE 1. Case outline continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS
35、, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Description 1 BOOT Boost capacitor for the high side field effect transistor (FET) gate driver. Connect 0.01 F low equivalent series resistance (ESR) capacitor from BOOT pi
36、n to PH pin. 2 NC Not connected internally. 3 NC Not connected internally. 4 VSENSE Feedback voltage for the regulator. Connect to output voltage divider. 5 ENA On/off control. Below 0.5 V, the device stops switching. Float the pin to enable. 6 GND Ground. Connect to thermal pad. 7 VINInput supply v
37、oltage. Bypass VINpin to GND pin close to device package with a high quality low ESR ceramic capacitor. 8 PH Source of the high side power metal oxide semiconductor field effect transistor (MOSFET). Connected to external inductor and diode. 9 POWER PAD GND pin must be connected to the exposed pad fo
38、r proper operation. FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 10 FIGURE 3. Block diagram. Provided by IHSNot
39、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09625 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection
40、 and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packa
41、ging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data cont
42、ained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) o
43、f supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Output voltage Package 3/ Vendor part number V62/09625-01XE 01295 Adjustable to 1.22 V
44、Thermally enhanced TPS5430MDDAREP 4/ 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturers data sheet
45、. 3/ Package drawings, thermal data, and symbolization are available from the manufacturer. 4/ The manufacture has changed lead frames NiPdAu to NiPdAuAg and location of assembly from their Hana facility to their Shanghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a NiPdAu fra
46、me from the Hana facility. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
