1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH
2、 PITHADIA TITLE MICROCIRCUIT, LINEAR, CMOS, MICROPOWER, STEP UP SWITCHING VOLTAGE REGULATOR, MONOLITHIC SILICON 11-06-29 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09637 REV PAGE 1 OF 10 AMSC N/A 5962-V054-11 Provided by IHSNot for ResaleNo reproduction or networking perm
3、itted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a CMOS micropower, step up switching voltage regulator microcircuit, with an operating temperature r
4、ange of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09637 - 01 X B Drawing Device type Ca
5、se outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX630 CMOS micropower, step up switching voltage regulator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 P
6、ackage style X 8 MS-012-AA Small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for
7、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VS) 18 V Input voltage (LBR, CX, IC, VFBpins) -0.3 V to (+VS+ 0.3 V) Output volta
8、ge, LX and LBD 18 V LX output current 525 mA (peak) LBD output current . 50 mA Power dissipation (PD) . 441 mW 2/ Junction temperature range (TJ) 150C Storage temperature range (TSTG) -65C to +160C Lead temperature (soldering, 10 seconds) . +300C Electrostatic discharge (ESD): Human body model (HBM)
9、 . 2,000 V Moisture sensitivity level (MSL) Level 1 1.4 Recommended operating conditions. 3/ Supply voltage (VS) . +6.0 V Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal data table. Case outline letter X X Units PC board Single layer Multi-layer 4/ Power dissipation (PD), maxim
10、um at +70C 471 606 mW Power dissipation (PD) derating above +70C 5.9 7.6 mW/C Thermal resistance, junction to case (JC) 40 38 C/W Thermal resistance, junction to ambient (JA) 170 132C/W 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These a
11、re stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Derate 5.88 mW/C above
12、+50C. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Package thermal resistances were obtained using the method desc
13、ribed in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO
14、. 16236 DWG NO. V62/09637 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the JEDEC Office, 3103 Nort
15、h 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C.
16、 ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as s
17、pecified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal
18、connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol C
19、onditions +VS= +6.0 V, IC= 5.0 A unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Supply voltage +VSOperating +25C 01 2.0 16.5 V Startup 1.9-55C to +125C 2.2 16.5 Internal reference voltage VREF+25C 01 1.29 1.33 V -55C to +125C 1.25 1.37 Switch current ISWV3= 400 mV +25C 01
20、75 mA Supply current at +VSpin ISI3= 0 mA +25C 01 125 A -55C to +125C 200 Efficiency +25C 01 85 typical % Line regulation 0.5 VOUT VS VOUT2/ +25C 01 0.2 %VOUT-55C to +125C 0.5 Load regulation VS= +5 V, PL= 0 to 150 mW 2/ +25C 01 0.5 %VOUTVS= 0.5VO, PL= 0 to 150 mW 2/ -55C to +125C 1.0 Operating freq
21、uency range FO3/ +25C 01 0.1 75 kHz Reference set internal pulldown resistance RICV6= VS+25C 01 0.5 10 M -55C to +125C 0.3 10 Reference set input voltage threshold VIC-55C to +125C 01 0.2 1.3 V Switch current ISWV3= 1.0 V +25C 01 100 mA Switch leakage current ICOV3= 16.5 V +25C 01 1.0 A -55C to +125
22、C 30 Supply current (shutdown) ISOIC 0.01 A +25C 01 1.0 A -55C to +125C 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 6 TA
23、BLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions +VS= +6.0 V, IC= 5.0 A unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Low battery bias current ILBR+25C 01 10 nA Capacitor charging current ICX+25C 01 30 typical A CX+threshold voltage +25C
24、01 +VS 0.1 typical V CX-threshold voltage +25C 01 0.1 typical V VFBinput bias current IFB+25C 01 10 nA Low battery detector output current ILBDV8= 0.4 V, V1= 1.1 V -55C to +125C 01 250 A Low battery detector output leakage ILBDOV8= 16.5 V, V1= 1.4 V +25C 01 5.0 A 1/ Testing and other quality control
25、 techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product per
26、formance is assured by characterization and/or design. 2/ Guaranteed by correlation with DC pulse measurements. 3/ The operating frequency range is guaranteed by design and verified with sample testing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,
27、-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 7 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62
28、/09637 REV PAGE 8 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 b 0.014 0.019 0.35 0.49 c 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 e 0.050 BSC 1.27 BSC E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1
29、.27 n 8 8 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Dimensions D and E do not include mold flash. 3. Mold flash or protrusions do not exceed 0.15 mm (0.006 inch). 4. Leads to be coplanar within 0.10 mm (.004 inch). 5. Falls within reference to
30、JEDEC MS-012-AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 9 Device type 01 Case outline X Terminal number Terminal
31、symbol Description 1 LBR Low battery detection comparator input. The LBD output, pin 8, sinks current whenever this pin is below the low battery detector threshold, typically 1.31 V 2 CXAn external capacitor connected between this terminal and ground sets the oscillator frequency. 47 pF = 40 kHz. 3
32、LXThis pin drives the external inductor. The internal N-channel metal oxide semiconductor field effect transistor (MOSFET) that drives LXhas an output resistance of 4 and a peak current rating of 525 mA. 4 GND Ground. 5 +VSThe positive supply voltage, from 2.0 V to 16.5 V. 6 ICThe device will shut d
33、own when this pin is left floating or is driven below 0.2 V. For normal operation, connect ICdirectly to +VSor drive it high with either a CMOS gate or pullup resistor connected to +VS. The supply current is typically 10 nA in the shutdown mode. 7 VFBThe output voltage is set by an external resistiv
34、e divider connected from the converter output to VFBand ground. The device will pulse the LXoutput whenever the voltage at this terminal is less than 1.31 V. 8 LBD The low battery detector output is an open-drain N-channel MOSFET that sinks up to 600 A (typical) whenever the LBR input, pin 1, is bel
35、ow 1.31 V. FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09637 REV PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufact
36、urer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATIO
37、N FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1
38、minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of su
39、pply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number 2/ V62/09637-01XB 1ES6
40、6 MAX630MSA/PR 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Add “-T” suffix for tape and reel. CAGE code Source of supply 1ES66 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086-5125 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
