1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 48 49 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARE
2、D BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, DIGITAL MEDIA SYSTEM ON CHIP (DMSoC), MONOLITHIC SILICON 10-04-06 APPROVED BY Thomas M. Hess SIZE A CODE IDENT.
3、NO. 16236 DWG NO. V62/09643 REV PAGE 1 OF 49 AMSC N/A 5962-V039-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 2 1. SCOPE 1.1 Scope. This drawi
4、ng documents the general requirements of a high performance Digital Media System on Chip (DMSoC) microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing est
5、ablishes an administrative control number for identifying the item on the engineering documentation: V62/09643 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Clock Rat Circuit function 01 SM320DM355-EP 216
6、 MHz Digital Media System on Chip (DMSoC) 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 337 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufac
7、turer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Provided by IHSNot for ResaleNo reproduction or networking
8、permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 3 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage ranges: All 1.3 V supplies . -0.5 V to 1.7 V All digital 1.8 V supplies . -0.5 V to 2.8 V All analog 1.8 V
9、 supplies -0.5 V to 1.89 V All 3.3 V supplies . -0.5 V to 4.4 V Input voltage ranges, (VI): All 1.8 V I/Os -0.5 V to 2.3 V All 3.3 V I/Os -0.5 V to 3.8 V VBUS . 0.0 V to 5.5 V Clamp current for input or output, (Iclamp) -20 mA to +20 mA 4/ Operating case temperature ranges, (TC): Device type: 01 -55
10、C to +125C Storage temperature range, (TSTG) -65C to +150C 1.4 Recommended operating conditions. 5/ Supply voltage: Supply voltage, Core (CVDD) 1.235 V to 1.365 V Supply voltage, PLL1 (VDDA_PLL1) . 1.235 V to 1.365 V Supply voltage, PLL2 (VDDA_PLL2) . 1.235 V to 1.365 V Supply voltage, USB digital (
11、VDDD13_USB) 1.235 V to 1.365 V Supply voltage, USB analog (VDDA13_USB) . 1.235 V to 1.365 V Supply voltage, USB analog (VDDA33_USB) . 3.135 V to 3.465 V Supply voltage, USB common PLL (VDDA33_USB_PLL) . 3.135 V to 3.465 V Supply voltage, DDR2/MDDR (VDD_DDR) 1.71 V to 1.89 V Supply voltage, DDR DLL A
12、nalog (VDDA33_DDRDLL) 3.135 V to 3.465 V Supply voltage, Digital video in (VDD_VIN) 3.135 V to 3.465 V Supply voltage, Digital video out (VDD_VOUT) . 3.135 V to 3.465 V Supply voltage, DAC analog (VDDA18_DAC) 1.71 V to 1.89 V Supply voltage, I/Os (VDD) 3.135 V to 3.465 V Supply ground: Supply ground
13、, Core, USB digital (VSS) . 0 V Supply ground, PLL1 (VSSA_PLL1) 0 V Supply ground, PLL2 (VSSA_PLL2) 0 V Supply ground, USB (VSS_USB) . 0 V Supply ground, DLL (VSSA_DLL) . 0 V Supply ground, DAC analog (VSSA_DAC) 0 V MXI1 osc ground, (VSS_MX1) 0 V MXI2 osc ground, (VSS_MX2) 0 V 6/ Supply ground, (VSS
14、) . 0 V 6/ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
15、Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. 4/ Clamp current flows from an input or putput pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current results from an applied
16、 input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage, VDD/VDDA_PLL1/2/VDD_USB/VDD_DDR for dual supply macros. Negative results from an applied voltage that is more than 0.5 V less (more negative) than the VSSvoltage. 5/ Use of this product beyond the manufa
17、cturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacit
18、or ground (see manufacturer data for more details). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 4 1.4 Recommended operating conditions - Continu
19、ed. Minimum high level input voltage, (VIH) 2.0 V 7/ Maximum low level input voltage, (VIL) . 0.8 V 7/ DAC: 8/ DAC reference voltage, (VREF) 450 TYP mV DAC full scale current adjust resistor, (RBIAS) 2550 TYP Output resistor, (RLOAD) . 499 TYP Bypass capacitor, (CBG) 0.1 TYP F Video buffer 8/ Output
20、 resistor (ROUT), between TVOUT and VFB pins (ROUT) . 1070 TYP Feed back resistor, between VFB and IOUT pins, (RFB) . 1000 TYP DAC full scale current adjust resistor, (RBIAS) 2550 TYP Bypass capacitor, (CBG) 0.1 F USB: USB external charge pump input (USB_VBUS) 4.85 V to 5.25 V USB reference resistor
21、, (R1) . 9.9 k to 10.1 k 9/ Operating case temperature (TC): 10/ Device type 01 -55C to +125C Thermal resistance characteristics for case outline X C/W 11/ Junction to case RJC7.2 Junction to board RJB11.4Junction to free air RJA27.0 Junction to package top PsiJT 0.1 Junction to board PsiJB 11.3 2.
22、APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still air). EIA/JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. EIA/J
23、ESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) _ 7/ These I/O specifications apply to regula
24、r 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os are 1.8 V I/Os and adhere to USB2.0 spec. 8/ See manufacturer data for more information. Also, resistors should be E-96 spec line (3 digits with 1% accuracy). 9/ Connect USB_R1 to VSS_USB_REF via 10 K, 1% resistor placed as close to the device as
25、possible. 10/ To avoid frequency performance device degradation, limit the total device power on hours to less than 16500 hrs at TC= 125C. 11/ The junction to case measurement was conducted in a JDEC defined 2S2P system and will change based on environment as well as application. For more informatio
26、n, see three EIA/JEDEC standards: EIA/JEDEC standards: 51-2, 51-3, 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 5 3. REQUIREMENTS 3.1 Marki
27、ng. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers pa
28、rt number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construc
29、tion, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in
30、 figure 3. 3.5.4 Test load circuit for AC timing measurement. The test load circuit for AC timing measurements shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 4-48. Provided by IHSNot for ResaleNo reproduction or networking permitted witho
31、ut license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition 2/ Device type: All Limits Unit Min Max Voltage output High level output voltage 3/ VOHDVDD=
32、MIN, IOH= MAX 2.4 V Low level output voltage 3/ VOLDVDD= MIN, IOL= MAX 0.6 Current Input/Output Input current for I/O without internal pull-up/pull-down IIVI= VSSto VDD-1 1 A Input current for I/O with internal pull-up 4/ 5/ II(pullup)VI= VSSto VDD40 190 Input current for I/O with internal pull-down
33、 4/ 5/ II(pulldown)VI= VSSto VDD-190 -40High level output current IOH-100 Low level output current IOL4000 I/O off state output current IOZVO= VDDor VSS, Internal pull disabled 10 TYP Capacitance Input capacitance CI4 pF Output capacitance CO4 DAC Resolution Resolution 10 TYP Bits Integral non-linea
34、rity, best fit INL RLOAD= 499 , Video buffer disabled 1 TYP LSB Differential non-linearity DNL 0.5 TYP Output compliance range Compliance RLOAD= 499 , IFS = 1.4 mA 0 0.700 V Video buffer Output high voltage (top of 75% NTSC or PAL colorbar) 6/ VOH(VIDBUF)1.55 TYP V Output low voltage (bottom of sync
35、 tip) VOL(VIDBUF)0.470 TYP RESET Timing requirements for Reset 7/ 8/ (See figure 5) No Test Symbol Test condition 2/ Device type: All Limits Unit Min Max 1 Active low width of the RESETnullnullnullnullnullnullnullnullnullpulse tw(RESET) 12C ns 2 Setup time, boot configuration pins valid before RESET
36、nullnullnullnullnullnullnullnullnullrising edge tsu(BOOT)12C3 Hold time, boot configuration pins valid after RESETnullnullnullnullnullnullnullnullnullrising edge th(BOOT)12COSCILLATORS AND CLOCKS Switching characteristics for 24 MHz system Start up time (from power up until oscillating at stable fre
37、quency) 4 ms Oscillation frequency 24 or 36 TYP MHz ESR 24 MHz 60 36 MHz 30 Frequency stability 50 ppm See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO.
38、 16236 DWG NO. V62/09643 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Device type: All Limits Unit Min Max OSCILLATORS AND CLOCKS - Continued Switching characteristics for 27 MHz system Start up time (from power up until oscillating at s
39、table frequency) 4 ms Oscillation frequency 27 TYP MHz ESR 50 Frequency stability 50 ppm CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks) Timing requirements for MXI1/CLKIN1 9/ 10/ 1 Cycle time, MXI1/CLKIN1 tc(MXI1)See figure 6 27.7 11/ 41.6 11/ ns 2 Pulse duration, MXI1/CLKIN1 high tw(MXI
40、1H)0.45C 0.55C3 Pulse duration, MXI1/CLKIN1 low tw(MXI1L)0.45C 0.55C4 Transition time, MXI1/CLKIN1 tt(MXI1)0.05C5 Period jitter, MXI1/CLKIN1 tJ(MXI1)0.02CTiming requirements for MXI2/CLKIN2 9/ 12/ 1 Cycle time, MXI2/CLKIN2 tc(MXI2)See figure 7 37.037 13/ 37.037 13/ ns 2 Pulse duration, MXI2/CLKIN2 h
41、igh tw(MXI2H)0.45C 0.55C3 Pulse duration, MXI2/CLKIN2 low tw(MXI2L)0.45C 0.55C4 Transition time, MXI2/CLKIN2 tt(MXI2)0.05C5 Period jitter, MXI2/CLKIN2 tJ(MXI2)0.02CSwitching characteristics for CLKOUT1 9/ 14/ 1 Cycle time CLKOUT1 tc(CLKOUT1)See figure 8 tc(MXI1)ns 2 Pulse duration, CLKOUT1 high tw(C
42、LKOUT1H)0.45P 0.55P 3 Pulse duration, C:LKOUT1 low tw(CLKOUT1L)0.45P 0.55P4 Transition time, CLKOUT1 tt(CLKOUT1)0.55P5 Delay time, MXI1/CLKIN1 high to CLKOUT1 high td(MXI1H-CLKOUT1H)1 8 6 Delay time, MXI1/CLKIN1 low to CLKOUT1 low td(MXI1L-CLKOUT1L)1 8 Switching characteristics for CLKOUT2 9/ 15/ 1
43、Cycle time CLKOUT2 tc(CLKOUT2)See figure 9 tc(MXI1)/3 ns 2 Pulse duration, CLKOUT2 high tw(CLKOUT2H)0.45P 0.55P 3 Pulse duration, C:LKOUT2 low tw(CLKOUT2L)0.45P 0.55P4 Transition time, CLKOUT2 tt(CLKOUT2)0.05P5 Delay time, MXI1/CLKIN1 high to CLKOUT2 high td(MXI1H-CLKOUT2H)1 8 6 Delay time, MXI1/CLK
44、IN1 low to CLKOUT2 low td(MXI1L-CLKOUT2L)1 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09643 REV PAGE 8 TABLE I. Electrical pe
45、rformance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Device type: All Limits Unit Min Max CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks) - Continued Switching characteristics for CLKOUT3 9/ 16/ 1 Cycle time CLKOUT3 tc(CLKOUT3)See figure 10 tc(MXI1)/8 ns 2 Pulse dura
46、tion, CLKOUT3 high tw(CLKOUT3H)0.45P 0.55P3 Pulse duration, C:LKOUT3 low tw(CLKOUT3L)0.45P 0.55P4 Transition time, CLKOUT3 tt(CLKOUT3)0.05P5 Delay time, CLKIN/MXI high to CLKOUT3 high td(MXI2H-CLKOUT3H)1 8 6 Delay time, CLKIN/MXI low to CLKOUT3 low td(MXI2L-CLKOUT3L)GPIO PERIPHERAL INPUT/OUTPUT ELEC
47、TRICAL DATA/TIMING Timing requirements for GPIO inputs 1 Pulse duration, GPIx high tw(GPIH)See figure 10 52 ns 2 Pulse duration, GPIx high tw(GPIL)52Switching characteristics for GPIO outputs 3 Pulse duration, GPOx high tw(GPOH)See figure 11 26 17/ ns 4 Pulse duration, GPOx low tw(GPOL)26 17/ GPIO P
48、ERIPHERAL EXTERNAL INTERRUPTS ELECTRICAL DATA/TIMING Timing requirements for external interrupts/EDMA events 18/ 1 Width of the external interrupt pulse low tw(ILOW)See figure 12 52 ns 2 Width of the external interrupt pulse high tw(IHIGH)52AEMIF ELECTRICAL DATA/TIMING Timing requirements for Asynchronous Memory Cycles for AEMIF module 19/ See figure 13 and 14 READS and WRITES 2 Pulse duration, EM_WAIT
