1、 REVISIONSLTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal dat
2、e of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS, MONOLITHIC SILICON 10-04-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/10612 REV PAGE 1 OF 12 AMSC N/A 5962-V042-10 .Provided by IHSNot for Resale
3、-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 8-bit shift registers with 3-state output registers microcircuit, with an operating temperature range
4、 of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10612 - 01 X E Drawing Device type Case o
5、utline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74HC595-EP 8-bit Shift Registers with 3-state output registers 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Pa
6、ckage style X 16 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absol
7、ute maximum ratings. 1/ Supply voltage range ( VCC) -0.5 V to 7 V Input clamp current ( IIK) ( VI 0 or VI VCC) . 20 mA 2/ Output clamp current ( IOK) ( VO 0 or VO VCC) . 20 mA 2/ Continuous output current ( IO) ( VO= 0 to VCC) . 35 mA Continuous current through VCCor GND . 70 mA Package thermal impe
8、dance ( JA) . 108C/W 3/ Storage temperature range (TSTG) . -65C to 150C _ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those ind
9、icated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal imped
10、ance is calculated in accordance with JESD 51-7. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range ( VCC) 2.0 V to 6.0 V Minimum high level input v
11、oltage ( VIH): VCC= 2 V . 1.5 V VCC= 4.5 V 3.15 V VCC= 6.0 V 4.2 V Maximum low level input voltage ( VIL): VCC= 2 V . 0.5 V VCC= 4.5 V 1.35 V VCC= 6.0 V 1.8 V Input voltage ( VI) 0 V to VCCOutput voltage ( VO) 0 V to VCCMaximum input transition rise or fall rate ( t / v ): 6/ VCC= 2.3 V to 2.7 V 200
12、 ns/V VCC= 3 V to 3.6 V . 100 ns/V VCC= 4.5 V to 5.5 V 20 ns/V Operating free-air temperature range ( TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mou
13、nt Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufactu
14、rer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there i
15、s a potential to do into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Provided by IHSNot
16、 for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE cod
17、e, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical per
18、formance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Te
19、rminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The Function table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Load circuit and timing waveforms. The load circuit and timing waveforms sha
20、ll be as shown in figure 5 . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHSDEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions
21、 unless otherwise specified VCCLimits Unit TA= 25C -55C TA 125C Min Max Min Max High level output voltage VOHVI= VIHor VILIOH= -20 A 2 V 1.9 1.9 V 4.5 V 4.4 4.4 6 V 5.9 5.9 QH, IOH= - 4 mA 4.5 V 3.98 3.7 QA QH, IOH= - 6 mA 3.98 3.7 QH, IOH= - 5.2 mA 6 V 5.48 5.2 QA QH, IOH= - 7.8 mA 5.48 5.2 Low lev
22、el output voltage VOLVI= VIHor VILIOL= 20 A 2 V 0.1 0.1 V 4.5 V 0.1 0.1 6 V 0.1 0.1 QH, IOL= 4 mA 4.5 V 0.26 0.4 QA QH, IOL= 6 mA 0.26 0.4 QH, IOL= 5.2 mA 6 V 0.26 0.4 QA QH, IOL= 7.8 mA 0.26 0.4 Input current IIVI= VCCor 0 6 V 100 1000 nA Off state output current IOZVO= VCCor 0, QA- QH6 V 0.5 10 A
23、Supply current ICCVI= VCCor 0, IO= 0 6 V 8 160 A In put capacitance Ci2 V to 6V 10 10 pF Power dissipation capacitance CpdNo load 400 TYP pF Timing requirements Clock frequency fclock2 V 6 4.2 MHz 4.5 V 31 21 6 V 36 25 Pulse duration twSRCL or RCLK high or low 2 V 80 120 ns 4.5 V 16 24 6 V 14 20 SRC
24、Lnullnullnullnullnullnullnulllow 2 V 80 120 4.5 V 16 24 6 V 14 20 Setup time tsuSER before SRCLK 2 V 100 150 4.5 V 20 30 6 V 17 25 SRCLK before RCLK 2 V 75 113 4.5 V 15 23 6 V 13 19 SRCLRnullnullnullnullnullnullnullnullnulllow before RCLK 2 V 50 75 4.5 V 10 15 6 V 9 13 SRCLRnullnullnullnullnullnulln
25、ullnullnullhigh (inactive) before SRCLK 2 V 50 75 4.5 V 10 15 6 V 9 13 See footnotes at end of table. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued.
26、 1/ Test Symbol Conditions unless otherwise specified VCCLimits Unit TA= 25C -55C TA 125C Min Max Min Max Timing requirements - Continued Hold time, SER after SRCLK th2 V 0 0 ns 4.5 V 0 0 6 V 0 0 Switching characteristics Maximum frequency CL= 50 pF 2 V 6 4.2 MHz 4.5 V 31 21 6 V 36 25 Propagation de
27、lay from SRCLK to QHtpd2 V 160 240 ns 4.5 V 32 48 6 V 27 41 Propagation delay from RCLK to QA-QHtpd2 V 150 225 4.5 V 30 45 6 V 26 38 Propagation delay, high to low, from SRCLRnullnullnullnullnullnullnullnullnullto QHtPHL2 V 175 261 4.5 V 35 52 6 V 30 44 Enable time from OEnullnullnullnullto QA-QHten
28、2 V 150 255 4.5 V 30 45 6 V 26 38 Disable time from OEnullnullnullnullto QA-QHtdis2 V 200 300 4.5 V 40 60 6 V 34 51 Transition time to QA-QHtt2 V 60 90 4.5 V 12 18 6 V 10 15 Transition time to QH2 V 75 110 4.5 V 15 22 6 V 13 19 Propagation delay from RCLK to QA-QHtpdCL= 150 pF 2 V 200 300 4.5 V 40 6
29、0 6 V 34 51 Enable time from OEnullnullnullnullto QA-QHten2 V 200 298 4.5 V 40 60 6 V 34 51 Transition time to QA-QHtt2 V 210 315 4.5 V 42 63 6 V 36 53 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature
30、 range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This setup time allows the storage register to receive
31、 stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 7 Case X D
32、imension Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.20 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 NOM 0.026 NOM c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 4.90 5.10 0.193 0.201 NOTES:
33、 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHSDE
34、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 8 Case X Terminal number Terminal symbol Terminal number Terminal symbol 1 QB9 QH 2 QC10 SRCLRnullnullnullnullnullnullnullnullnull3 QD11 SRCLK4 QE12 RCLK 5 QF13 OEnullnullnullnull6 QG14 SER 7 QH15 QA8
35、 GND 16 VCCFIGURE 2. Terminal connections. Inputs Function SER SRCLK SRCLRnullnullnullnullnullnullnullnullnullRCLK OEnullnullnullnullX X X X H Outputs QA QHare disable X X X X L Outputs QA QHare enable X X L X X Shift register is clear L H X X First stage of the shift register goes low. Other stage
36、store the data of previous stage, respectively H H X X First stage of the shift register goes high. Other stage store the data of previous stage, respectively X X X X Shift register data is stored in the storage register FIGURE 3. Function table. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENT
37、ER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 9 FIGURE 4. Logic diagram. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 10 FIGURE 5. Load circuit and timing waveforms. Provid
38、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHSDEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 11 NOTES: 1. CLincludes probe and text fixture capacitance. 2. Waveform 1 is for an output with internal condit
39、ions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied b
40、y generators having the following characteristics: PRR 1 MHz, ZO= 50 ,tr= 6 ns, and tf= 6 ns. 4. For clock inputs, fmax is measured when the input duty cycle is 50%. 5. The outputs are measured one at a time with one input transition per measurement. 6. tPLZand tPHZare the same as tdis. 7. tPZLand t
41、PZHare the same as ten. 8. tPHLand tPLHare the same as tpd. FIGURE 5. Load circuit and timing waveforms Continued. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10612 REV PAGE 12 4. VERIFICATION 4.1 Product assurance requirem
42、ents. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applica
43、ble. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classifie
44、d as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggest
45、ed source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top
46、side marking V62/10612-01XE 01295 SN74HC595MPWREP HC595EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for Resale-,-,-
