1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02 and case outline Y. - ro 13-02-14 C. SAFFLE B Make correction to ENBL pin and IN pin input voltage, delete -5 V and substitute -0.3 V as specified under paragraph 1.3. Delete power dissipation limit entirely from paragraph 1.3. - ro 13-05
2、-01 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.
3、dla.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, SINGLE 9 AMP HIGH SPEED LOW SIDE MOSFET DRIVER WITH ENABLE, MONOLITHIC SILICON 10-10-20 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11601 REV B PAGE 1 OF 16 AMSC N/A 5962-V053
4、-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single 9 amp
5、 high speed low side metal oxide semiconductor field effect transistor (MOSFET) with enable microcircuit, with an operating temperature ranges of -40C to +105C for device type 01 and -55C to +125C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the
6、 item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11601 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generi
7、c Temperature Circuit function 01 UCC27322-EP -40C to +105C Single 9 amp high speed low side MOSFET with enable 02 UCC27322-EP -55C to +125C Single 9 amp high speed low side MOSFET with enable 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB
8、 95 Package style X 8 MO-187-AA Plastic surface mount Y 8 MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium
9、 E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VDD) . -0.3 V to
10、 16 V Output current (OUT) . 0.6 A Input voltage (VI): IN pin -0.3 V to 6 V or VDD+ 0.3 V (whichever is larger) ENBL pin -0.3 V to 6 V or VDD+ 0.3 V (whichever is larger) Latch up protection . 500 mA Junction operating temperature range (TJ) : Device type 01 . -40C to +150C Device type 02 . -55C to
11、+150C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating conditions. 3/ Supply voltage range (VDD) . 4.5 V to 15 V Operating free-air temperature range (TA) : Device type 01 . -40C to +105C Device type 02 . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum r
12、ating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods m
13、ay affect device reliability. 2/ All voltages are within respect to GND. Currents are positive into and negative out of the specified terminal. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no
14、 responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 4 1.5 Thermal characteristics. Therm
15、al metric Symbol Case X Case Y Unit Thermal resistance, junction-to-ambient 4/ JA161.8 116.3 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)56.2 70.8 C/W Thermal resistance, junction-to-board 6/ JB81.1 56.6 C/W Characterization parameter, junction-to-top 7/ JT5.7 22.8 C/W Characterization
16、parameter, junction-to-board 8/ JB79.8 56.1 C/W _ 4/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (to
17、p) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to
18、 control the printed circuit board (PCB) temperature, as described in JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (se
19、ctions 6 and 7). 8/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction
20、 or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 5 2. APPLICABLE DOCUMENTS AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurem
21、ents for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) JEDEC Solid State Technology Association JEDE
22、C PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JESD51-7 - High Effe
23、ctive Thermal Conductivity Test Board for Leaded Surface Mount Packages. (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and l
24、egibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if
25、 applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as
26、 specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Truth table. The truth tabl
27、e shall be as shown in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE
28、 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VDD= 4.5 V to 15 VTemperature, TJ= TADevice type Limits Unit Min Max Overall characteristics. Static operating current IDDIN = low, ENBL = low, VDD= 15 V -40C to +105C 01 225 A IN = high, ENBL = low, VDD= 15 V 650 IN = low
29、, ENBL = high, VDD= 15 V 125 IN = high, ENBL = high, VDD= 15 V 1000 IN = low, ENBL = low, VDD= 15 V -55C to +125C 02 225 IN = high, ENBL = low, VDD= 15 V 650 IN = low, ENBL = high, VDD= 15 V 125 IN = high, ENBL = high, VDD= 15 V 1000 Input characteristics. Logic 1 input threshold VIH-40C to +105C 01
30、 2 V -55C to +125C 02 2 Logic 0 input threshold VIL-40C to +105C 01 1 V -55C to +125C 02 1 Input current IIN0 V VIN VDD-40C to +105C 01 -10 10 A -55C to +125C 02 -10 10 Output characteristics. Peak output 2/ 3/ current VDD= 14 V -40C to +105C 01 9 typical A High level output voltage VOHVOH= VDD- VOU
31、T, -40C to +105C 01 300 mV IOUT= -10 mA -55C to +125C 02 300 Low level output voltage VOLIOUT= 10 mA -40C to +105C 01 25 mV -55C to +125C 02 25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUM
32、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VDD= 4.5 V to 15 VTemperature, TJ= TADevice type Limits Unit Min Max Output characteristics continued. Output resistance 4/ high ROHIOUT= -10 mA,
33、VDD= 14 V -40C to +105C 01 25 -55C to +125C 02 25 Output resistance 4/ low ROLIOUT= 10 mA, VDD= 14 V -40C to +105C 01 2.5 -55C to +125C 02 2.5 Enable characteristics. Enable rising threshold voltage VEN_HLow to high transitions -40C to +105C 01 1.7 2.7 V -55C to +125C 02 1.5 3.4 Enable falling thres
34、hold voltage VEN_LHigh to low transitions -40C to +105C 01 1.1 2 V -55C to +125C 02 1.1 2.2 Hysteresis -40C to +105C 01 0.25 0.90 V -55C to +125C 02 0.18 1.15 Enable impedance R(ENBL)VDD= 14 V, ENBL = low -40C to +105C 01 75 135 k -55C to +125C 02 75 180 Propagation delay time tD3CLOAD= 10 nF, see f
35、igure 5 -40C to +105C 01 90 ns -55C to +125C 02 95 Propagation delay time tD4CLOAD= 10 nF, see figure 5 -40C to +105C 01 90 ns -55C to +125C 02 95 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME CO
36、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VDD= 4.5 V to 15 VTemperature, TJ= TADevice type Limits Unit Min Max Switching characteristics. See figure 5. Rise time (OUT) tRCLOAD= 10 nF -4
37、0C to +105C 01 70 ns -55C to +125C 02 77 Fall time (OUT) tFCLOAD= 10 nF -40C to +105C 01 30 ns -55C to +125C 02 35 Delay time, IN rising (IN to OUT) tD1CLOAD= 10 nF -40C to +105C 01 70 ns -55C to +125C 02 75 Delay time, IN falling (IN to OUT) tD2CLOAD= 10 nF -40C to +105C 01 70 ns -55C to +125C 02 7
38、5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of sp
39、ecific parametric testing, product performance is assured by characterization and/or design. 2/ Specified by design. 3/ The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET tr
40、ansistors. 4/ The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON)of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Provided by IHSNot for ResaleNo
41、 reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 9 Case X FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAN
42、D AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 10 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.043 - 1.10 A1 0.001 0.006 0.05 0.15 b 0.010 0.014 0.25 0.38 c 0.005 0.009 0.13 0.23 D 0.114 0.122 2.90 3.10 E 0.114 0.122 2.90 3.10 E
43、1 0.187 0.199 4.75 5.05 e 0.026 BSC 0.65 BSC L 0.015 0.027 0.40 0.70 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not
44、exceed 0.15 mm (0.006 inch) per side. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed (0.50 mm) 0.019 inch per side. 4. Falls within JEDEC MO-187-AA, except interlead flash. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reprodu
45、ction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 11 Case Y FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DL
46、A LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11601 REV B PAGE 12 Case Y continued. Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.069 - 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.17 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4
47、.00 E1 0.228 0.244 5.80 6.20 e 0.050 BSC 1.27 BSC L 0.016 0.050 0.40 1.27 n 8 8 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.15 mm (0.006 inch) per side. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed (0.50 mm) 0.019 inch per side. 4. Falls with JEDEC MS-0
