1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY Phu H
2、. Nguyen TITLE MICROCIRCUIT, DIGITAL, PHASE DETECTOR/ FREQUENCY SYNTHESIZER, MONOLITHIC SILICON 11-01-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11607 REV PAGE 1 OF 10 AMSC N/A 5962-V028-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
3、se from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Phase detector/ Frequency synthesizer microcircuit, with an operating temperature range of -55C to +
4、125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer,s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11607 - 01 X B Drawing Device type Case outline Lead
5、finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADF4002-EP Phase detector/ Frequency synthesizer 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-15
6、3 Lead Thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot f
7、or ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced : AVDDto GND 2/ . -0.3 V to +3.6 V AVDDto DVDD. -0.3 V to +0.3 V VPto GND 2/
8、 . -0.3 V to +5.8 V VPto AVDD-0.3 V to +5.8 V Digital I/O voltage to GND 2/ . -0.3 V to DVDD+ 0.3 V Analog I/O voltage to GND 2/ -0.3 V to VP+ 0.3 V REFIN, RFINA, REFINB to GND 2/ . -0.3 V to AVDD+ 0.3 V Ambient operating temperature range . -55C to +125C Storage temperature range . -65C to +150C Ma
9、ximum junction temperature (TJ) 150C Lead temperature, soldering: Vapor phase (60 sec) 215C Infrared (15 sec) . 220C Transistor count: CMOS 6425 Bipolar 303 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to
10、 the Electronic Industries Alliance, North 10thSt., Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE
11、 code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical
12、 performance characteristics are as specified in 1.3, 1.4, and table I herein. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond thos
13、e indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ GND = AGND = DGND = 0 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAN
14、D AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure
15、 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Timing diagrams. The timing diagrams shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction o
16、r networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ unless otherwise specified Limits Unit Min Max RF characteristics RF in
17、put sensitivity -10 0 dBm RF Input frequency RFINFor RFIN4V/s 5 400 MHz REFINcharacteristics REFINinput frequency For REFIN50 V/s 20 300 MHz REFINinput sensitivity 3/ Biased at AVDD/2 (ac coupling ensures AVDD/2 bias) 0.8 AVDDVp-p REFINinput capacitance 10 pF REFINinput current 100 A Phase Frequency
18、 detector Phase detector frequency 4/ ABP2:1 = 00 (2.9 ns antibacklash pulse width) 104 MHz Charge pump Sink/Source High value Low value Absolute accuracy RSETrange ICPRSET= 5.1 k 5 TYP mA 625 TYP A RSET= 5.1 k 2.5 TY % 3.0 11 k Three stage leakage ICPTA= 25C 1 TYP nA ICPvs VCP0.5 VCP (VP 0.5 V) 1.5
19、 TYP % Sink and source current matching 0.5 VCP (VP 0.5 V) 2 TYP % ICPvs temperature VCP= VP/2 2 TYPLogic inputs Input high voltage VIH1.4 V Input low voltage VIL0.6 Input current IINH, IINL1 A Input capacitance CIN10 pF Logic outputs Output high voltage VOHOpen-drain output, 1 k pull up resistor to
20、 1.8 V CMOS output chosen 1.4 V VDD 0.4 Output high current IOH100 A Output low voltage VOLIOL= 500 A 0.4 V Power supplies AVDD2.7 3.3DVDDAVDDV VPAVDD VP 5.5 V AVDD5.5 V IDD(AIDD+DIDD) 5/ 6.0 mA IP TA = 25C 0.4 Power down mode AIDD+ DIDD1 TYP A See footnotes at end of table. Provided by IHSNot for R
21、esaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specified Limits Unit M
22、in Max Noise characteristics Normalized phase noise floor (PNSYNTH) 6/ 7/ PLL loop BW = 500 kHz -222 TYP dBc/Hz Normalized 1/f Noise (PN1_f) 6/ 8/ Measured at 10 kHz offset, normalized to 1 GHz -122 TYP Timing characteristics 9/ 10/ Data to clock setup time t110 ns Data to clock hold time t210 Clock
23、 high duration t325 Clock low duration t425 Clock to LE setup time t510 LE pulse width t620 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the ful
24、l temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ AVDD= DVDD= 3 V 10%, AVDD VP 5.5 V, AGND = DGND = CPGND = 0 V, RSET= 5.1 k, dBm referred to 50 , -55C TA +125C, un
25、less otherwise noted. 3/ AVDD= DVDD= 3.0 V. 4/ Guaranteed by design. Sample tested to ensure compliance. 5/ TA= 25C; AVDD= DVDD= 3 V; RFIN= 350 MHz. The current for any other setup (25C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF); RF frequency and REFINfrequency in MHz. 6/ All phas
26、e noise measurements were performed with a Rohde the two LSBs are the control bits. This input is a high impedance CMOS input. 13 LE Load Enable. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. This input
27、 is a high impedance CMOS input. 14 MUXOUT Multiplexer Output. This output allows the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. 15 DVDDDigital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be
28、placed as close as possible to the DVDDpin. DVDDmust be the same value as AVDD. 16 VPCharge Pump Power Supply. This should be greater than or equal to AVDD. In systems where AVDDis 3 V, VPcan be set to 5.5 V and used to drive a VCO with a tuning voltage of up to 5 V. FIGURE 3. Pin Function Descripti
29、ons. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 9 FIGURE 3. Functional block diagram. FIGURE 4. Timing diagram. Provided by IHSNot for ResaleNo reproduct
30、ion or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11607 REV PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated
31、 in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall b
32、e in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salien
33、t characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be constr
34、ued as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/11607-01XB 24355 ADF4002SRU-EP-RL7 1/ The vendor item drawing establishes an administrative control nu
35、mber for identifying the item on the engineering documentation. CAGE code Source of supply 24355 Analog Devices Rt 1 Industrial Park PO Box 9106 Norwood, MA 02062 Point of contact: 7910 Triad Center Drive Greensboro, NC 27409-9605 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
