1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www
2、.landandmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICROCONTROLLER, MONOLITHIC SILICON 12-12-10 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12621 REV A PAGE 1 OF 23 AMSC N/A 5962-V076-12 Provided by I
3、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller mi
4、crocircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation
5、: V62/12621 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430G2231-EP Mixed signal microcontroller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Numb
6、er of pins JEDEC PUB 95 Package style X 8 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash
7、 palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS. -0.3 V to 4.1 V Voltage ap
8、plied to any pin -0.3 V to VCC+0.3 V 2/ Diode current at any device terminal 2 mA Storage temperature: 3/ Unprogrammed device -55C to 150C Programmed device -55C to 150C 1.4 Recommended operating conditions. Supply voltage, (VCC): During program execution . 1.8 V to 3.6 V During flash program/erase
9、. 2.2 V to 3.6 V Supply voltage, (VSS) 0 V Operating free air temperature, (TA) . -40C to 125C Processor frequency (Maximum MCLK frequency) 4/ 5/ VCC= 1.8 V, Duty cycle = 50% 10% dc to 6 MHz VCC= 2.7 V, Duty cycle = 50% 10% dc to 12 MHz VCC= 3.3 V, Duty cycle = 50% 10% dc to 16 MHz 2. APPLICABLE DOC
10、UMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. (Copies of these documents are available onlin
11、e at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of t
12、he device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltage values referenced to VSS. The JTAG fuse blow voltage, VFBis allo
13、wed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse 3/ Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label
14、 on the shipping boxes or reels. 4/ The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 5/ Modules might have different maximum input clock specification. See the specification from the manufacturer dat
15、a sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers p
16、art number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical cha
17、racteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1
18、 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shal
19、l be as shown in figure 4. 3.5.5 Safe operating area. The safe operating area shall be as shown in figure 5. 3.5.6 POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown in figure 6. 3.5.7 VCC(drop) level with a Square voltage drop to gernerate a
20、 POR/Brownout signal. The VCC(drop) level with a Square voltage drop to gernerate a POR/Brownout signal shall be as shown in figure 7. 3.5.8 VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout s
21、ignal shall be as shown in figure 8. 3.5.9 DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time from LPM3/4 vs DCO frequency waveforms shall be as shown in figure 9. 3.5.10 USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as s
22、hown in figure 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ 4/ TAVCC
23、Limits Unit Min Max Active mode supply current into VCCexcluding external current Active mode (AM) current (1 MHz) IAM, 1MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 0, SCG0 = 0 SCG1 = 0, OSCOOFF = 0 2.2 V 220 TYP A
24、3 V 390 Low power mode Supply current (into VCC) Excluding external current Low power mode 0 (LPM0) current 5/ ILPM0, 1MHzfMCLK= 0 MHz, fSMCLK= fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25C 2.2 V 65 TYP A Low power mode 2 (
25、LPM2) current 6/ ILPM2fMCLK= fSMCLK= 0 MHz, fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25C 2.2 V 22 TYP 125C 46 Low power mode 3 (LPM3) current 6/ ILPM3, LFXT1fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 32768 Hz, CPUOFF = 1, SCG0 = 1
26、, SCG1 = 1, OSCOFF = 0 25C 2.2 V 1.5 125C 21 Low power mode 3 (LPM3) current 6/ ILPM3, VLOfDCO= fMCLK= fSMCLK= 0 MHz, fACLK= from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25C 2.2 V 0.7 125C 9.3 Low power mode 4 (LPM4) current 7/ ILPM4fDCO= fMCLK= fSMCLK= 0 MHz, fACLK=
27、 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 25C 2.2 V 0.5 85C 1.5 125C 7.1 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE
28、 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max Schmitt Trigger inputs (Port Px) 42/ Positive going input threshold voltage VIT+0.45 VCC0.75 VCCV 3 V 1.35 2.25 Negative going input threshold voltage VIT-0.25 VCC0.55 VCC3 V 0.75 1.65
29、 Input voltage hysteresis (VIT+- VIT-) Vhys3 V 0.3 1.0 Pullup/pulldown resistor RPullFor pullup: VIN= VSSFor pulldown: VIN= VCC3 V 20 50 k Input capacitance CIVIN= VSSor VCC5 TYP pF Leakage current (Port Px) High impedance leakage current Ilkg(Px.y)TA= 125C 8/ 9/ 3 V +120 nA TA= -40C to 105C 8/ 9/ 5
30、0 Outputs (Port Px) High level output voltage VOHI(OHmax)= -6 mA 10/ 3 V VCC 0.3 TYP Low level output voltage VOLI(OLmax)= 6 mA 10/ 3 V VCC+ 0.3 TYP Output frequency (Port Px) Port output frequency (with load) fPx.yPx.y, CL= 20 pF, RL= 1 k 11/ 12/ 3 V 12 TYP MHz Clock output frequency fPortCLKPx.y,
31、CL = 20 pF 12/ 3 V 16 TYP POR/Brownout reset (BOR) 13/ 42/ See figure 10 VCC(start)dVCC/dt 3 V/s 0.7 x V(B_IT-)TYP V See figure 10 through figure 12 V(B_IT-)dVCC/dt 3 V/s 1.35 TYP V See figure 10 Vhys(B_IT-)dVCC/dt 3 V/s 130 TYP mV See figure 10 td(BOR)2000 s Pulse length needed at RST/NMI pin to ac
32、cept reset internally t(reset)2.2V/3 V 2 s See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 7 TABLE I. Electrical performance cha
33、racteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max DCO frequency Supply voltage VCCRSELx VEREF-, SREF1 = 1, SREF0 = 0 1.4 VCCV VEREF- VEREF+ VCC 0.15 V, SREF1 = 1, SREF0 = 1 27/ 1.4 3 Negative external reference input voltage range 28/ VEREF- VEREF+ VEREF- 0 1.2 V Differen
34、tial external reference input voltage range, VEREF = VEREF+ - VEREF- VEREF VEREF+ VEREF- 29/ 1.4 VCCV Static input current into VEREF+ IVEREF+0 V VEREF+ VCC, SREF1 = 1, SREF0 = 0 3 V 1 TYP A 0 V VEREF+ VCC 0.15 V 3 V, SREF1 = 1, SREF0 = 1 27/ 3 V 0 TYP Static input current into VEREF- IVEREF-0 V VER
35、EF- VCC3 V 1 TYP A See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 12 TABLE I. Electrical performance characteristics - Continue
36、d. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max 10 Bit ADC, Timing parameters 42/ ADC10 input clock frequency fADC10CLKFor specified performance of ADC10 linearity parameters ADC10SR = 0 3 V 0.45 6.3 MHz ADC10SR = 1 0.45 1.5 ADC10 built in oscillator frequency fADC10OSCADC10DIVx = 0, ADC10SSE
37、Lx = 0, fADC10CLK= fADC10OSC3 V 3.7 6.3 MHz Conversion time tCONVERTADC10 built in oscillator, ADC10SSELx = 0, fADC10CLK= fADC10OSC3 V 2.06 3.51 s fADC10CLKfrom ACLK, MCLK, or SMCLK: ADC10SSELx 0 13 x ADC10DIV x 1/fADC10CLKTurn on setting time of the ADC tADC10ON30/ 100 ns 10 Bit ADC, Linearity para
38、meters 42/ Integral linearity error EI3 V 1 LSB Differential linearity error ED3 V 1 Offset error EOSource impedance RS 100 3 V 1 Gain error EG3 V 2 Total unadjusted error ET3 V 5 10 Bit ADC, Temperature sensor and built in VMID 42/ Temperature sensor supply current 31/ ISENSORREFON = 0, INCHx = 0Ah
39、, TA= 25C 3 V 60 TYP A TCSENSORADC10ON = 1 INCHx = 0Ah 32/ 3 V 3.55 TYP mV/C Sample time required if channel 10 is selected 33/ tSensor(sample)ADC10ON = 1 INCHx = 0Ah, Error of conversion result 1 LSB 3 V 30 s Current into divider at channel 11 IVMIDADC10ON = 1 INCHx = 0Bh 3 V 34/ A VCCdivider at ch
40、annel 11 VMIDADC10ON = 1 INCHx = 0Bh, VMID 0.5 x VCC3 V 1.5 TYP V Sample time required if channel 11 is selected 35/ tVMID(sample)ADC10ON = 1 INCHx = 0Bh, Error of conversion result 1 LSB 3 V 1220 ns See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted w
41、ithout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 13 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max Flash memory 42/ Program and erase supply voltage VCC(PGM/ERASE)
42、2.2 3.6 V Flash timing generator frequency fFTG257 476 kHz Supply current from VCCduring program IPGM3 V 5 mA Supply current from VCCduring erase IERASE3 V 7 mA Cumulative program time 36/ tCPT2.2 V/3.6 V 10 ms Cummulative mass erase time tCMErase2.2 V/3.6 V 20 ms Program/erase endurance -40C TJ 105
43、C 104cycles Data retention duration tRetentionTJ= 25C 15 years Word or byte program time tWord37/ 30 TYP tFTGBlock program time for first byte or word tBlock, 037/ 25 TYP Block program time for each additional byte or word tBlock, 1-6337/ 18 TYP Block program end sequence wait time tBlock, End37/ 6
44、TYP Mass erase time tMass Erase37/ 10593 TYP Segment erase time tSeg Erase37/ 4819 TYP RAM RAM retention supply voltage 38/ V(RAMh)CPU halted 1.6 V JTAG and Spy-Bi-Wire Interface Spy-Bi-Wire input frequency fSBW2.2 V/3 V 0 20 MHz Spy-Bi-Wire low clock pulse length tSBW,Low2.2 V/3 V 0.025 15 s Spy-Bi
45、-Wire enable time (Test high to acceptance of first clock edge 39/) tSBW,En2.2 V/3 V 1 s Spy-Bi-Wire return to normal operation time tSBW,RetTA= -40C to 105C 2.2 V/3 V 15 100 s TCK input frequency 40/ fTCK2.2 V 0 5 MHz 3 V 0 10 MHz Internal pulldown resistance on TEST RInternalTA= -40C to 105C 2.2 V
46、/3 V 25 90 k See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12621 REV PAGE 14 TABLE I. Electrical performance characteristics - Continued. 1/
47、Test Symbol Conditions 2/ VCCLimits Unit Min Max JTAG fuse 41/ 43/ Supply voltage during fuse blow condition VCC(FB)2.5 V Voltage level on TEST for fuse blow VFB6 7 V Supply current into TEST during fuse blow IFB100 mA Time to blow fuse tFB1 ms 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric tes
