1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original d
2、ate of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, SINGLE 3-INPUT POSITIVE OR-AND GATE, MONOLITHIC SILICON 13-02-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13605 REV PAGE 1 OF 11 AMSC N/A 5962-V045-13 Provided by IHSNot for ResaleNo reproduction
3、 or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single 3-input positive OR-AND gate microcircuit, with an oper
4、ating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/13605 - 01 X E Dra
5、wing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC1G3208-EP Single 3-input positive OR-AND gate 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDE
6、C PUB 95 Package style X 6 JEDEC MO-178-Variation AB Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold
7、 flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high impedance or power-off state (VO) . -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high
8、or low state (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Maximum input clamp current (IIK) (VI 0) -50 mA Maximum output clamp current (IOK) (VO 0) -50 mA Maximum continuous output current (IO) . 50 mA Maximum continuous current through VCCor GND . 100 mA Package thermal impedance (JA): 207C/W 4/ Storage tempe
9、rature range (TSTG) . -65C to 150C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating con
10、ditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended
11、operating conditions table. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 3 1.4
12、 Recommended operating conditions. 5/ 6/ Supply voltage (VCC): Operating . 1.65 V to 5.5 V Data retention only 1.5 V minimum Minimum high-level input voltage (VIH): VCC= 1.65 V to 1.95 V . 0.65 x VCCVCC= 2.3 V to 2.7 V . 1.7 V VCC= 3 V to 3.6 V 2 V VCC= 4.5 V to 5.5 V . 0.7 x VCCMaximum low-level in
13、put voltage (VIL): VCC= 1.65 V to 1.95 V . 0.35 x VCCVCC= 2.3 V to 2.7 V . 0.7 V VCC= 3 V to 3.6 V 0.8 V VCC= 4.5 V to 5.5 V . 0.3 x VCCInput voltage (VI) . 0 V to 5.5 V Output voltage (VO) . 0 V to VCCMaximum high-level output current (IOH): VCC= 1.65 V -4 mA VCC= 2.3 V -8 mA VCC= 3 V . -16 mA VCC=
14、 3 V . -24 mA VCC= 4.5 V -32 mA Maximum low-level output current (IOL): VCC= 1.65 V 4 mA VCC= 2.3 V 8 mA VCC= 3 V . 16 mA VCC= 3 V . 24 mA VCC= 4.5 V 32 mA Input transition rise or fall rate (t/V): VCC= 1.8 V 0.15 V, 2.5 V 0.2 V . 20 ns/V VCC= 3.3 V 0.3 V . 10 ns/V VCC= 5 V 0.5 V 5 ns/V Operating fr
15、ee-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents a
16、re available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 5/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and fu
17、nctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 6/ All unused inputs of the device must be held at VCCor
18、 GND to ensure proper device operation. Refer to the manufacturer application report, implications of slow or floating CMOS inputs, literature number SCBA004. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A
19、 CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2
20、Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I he
21、rein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in fig
22、ure 2. 3.5.3 Function table. The function table shall be as shown in figure 3. 3.5.4 Logic diagram (Positive). The logic diagram (Positive) shall be as shown in figure 4. 3.5.5 Function selection table. The function selection table shall be as shown in figure 5. 3.5.6 Logic configurations. The logic
23、 configurations shall be as shown in figure 6. 3.5.7 Load circuit and voltage waveforms. The load circuit and voltage waveforms shall be as shown in figure 7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A
24、 CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ VCCLimits Unit Min Typ 3/ Max High level output voltage VOHIOH= - 100 A 1.65 V to 5.5 V VCC 0.1 V IOH= - 4 mA 1.65 V 1.2 IOH= - 8 mA 2.3 V 1.9 IOH= - 16 mA 3 V 2.4 IO
25、H= - 24 mA 2.3 IOH= - 32 mA 4.5 V 3.8 Low level output voltage VOLIOL= 100 A 1.65 V to 5.5 V 0.11 V IOL= 4 mA 1.65 V 0.52 IOL= 8 mA 2.3 V 0.45 IOL= 16 mA 3 V 0.68 IOL= 24 mA 1.1 IOL= 32 mA 4.5 V 1.1 Input current A, B, or C inputs IIVI = 5.5 V or GND 0 to 5.5 V -12.05 8.6 A Offset current IoffVIor V
26、O= 5.5 V 0 -22 41.5 A Supply current ICCVI = 5.5 V or GND IO= 0 1.65 V to 5.5 V 12.5 A Supply current change ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 5.5 V 500 A Input capacitance CiVI= VCCor GND 3.3 V 3.5 pF Test Symbol From (Input) To (Output) VCC= 1.8 V 0.15 V VCC= 2.5 V 0.2 V
27、VCC= 3.3 V 0.3 V VCC= 5 V 0.5 V Unit Min Max Min Max Min Max Min Max Switching characteristics 2/ CL= 15 pF See FIGURE 7a. Propagation delay time tpdA, B, or C Y 3.7 14 2.5 7 1.7 5 1.3 3.4 ns Switching characteristics 2/ CL= 30 pF or 50 pF See FIGURE 7b. Propagation delay time tpdA, B, or C Y 2.5 17
28、.5 1.8 7.6 1.8 5.9 0.8 4.5 ns Test Symbol Test conditions VCC= 1.8 V VCC= 2.5 V VCC= 3.3 V VCC= 5 V Unit TYP TYP TYP TYP Operating characteristics TA= 25C Power dissipation capacitance Cpdf = 10 MHz 15 15 16 17 pF 1/ Testing and other quality control techniques are used to the extent deemed necessar
29、y to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or des
30、ign. 2/ Over free air temperature range (unless otherwise noted). 3/ All typical values are at VCC= 3.3 V, TA= 25C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV
31、 PAGE 6 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.45 E 1.45 1.75 A1 0.00 0.15 E1 2.60 3.00 b 0.25 0.50 e 0.95 BSC c 0.08 0.22 L 0.30 0.55 D 2.75 3.95 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body len
32、gth does not include mold flash, or protrusions. Mold flash and protrusions shall not exceed 0.15 per side. 4. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. 5. Falls within JEDEC MO-178 Variation AB, except minimum lead width. FIGURE 1. Case outline. 1 36 4Db6 PLS0.20 ME E1e
33、AA1SEATINGPLANE0.10SEEDETAIL ADETAIL A0-8GAGEPLANEL1cL5PIN 1INDEX AREAProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 7 Case outline X Terminal number Termina
34、l symbol Terminal number Terminal symbol 1 A 6 C 2 GND 5 VCC 3 B 4 Y FIGURE 2. Terminal connections. Inputs Output Y A B C H X H H X H H H X X L L L L H L FIGURE 3. Function table. FIGURE 4. Logic diagram (Positive). Logic Function Figure 2-input AND gate See FIGURE 6a 2-input OR gate See FIGURE 6b
35、Y = (A + B)C See FIGURE 6c FIGURE 5. Function selection table. ABCYProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 8 2-inpu AND gate FIGURE 6a. Logic configur
36、ations. 2-input OR gate FIGURE 6b. Logic configurations. Y = (A + B) C FIGURE 6c. Logic configurations. BCYCCVBCY A CYCCVACYAYCCVABYBAYCCVABYBCCProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO.
37、 16236 DWG NO. V62/13605 REV PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, exce
38、pt when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 . 4. The output are measured one at a time, with one transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7.
39、 tPLHand tPHLare the same as tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 7a. Load circuit and voltage waveforms. tPZLtPLZtPHZtPZHVOLVOHV0 VOUTPUTtPLHtPHLtPLHtPHLVOHOUTPUTVOLINPUTVOHVOLLOAD0 VtwtsuthDATAINPUTINPUTVTIMINGINPUTOUTPUTWAVEFORM 1S1 AT VOUTPUTWAVEFORM 2S1
40、 AT GNDSEE NOTE 2VOLLOADSEE NOTE 2IVM0 VVIVM0 VVIVM0 VVIVMVMVMVMVM0 VVIVMOHVOLTAGE WAVEFORMSPULSE DURATIONVOLTAGE WAVEFORMSSETUP AND HOLD TIMESCLFROM OUTPUTUNDER TESTOPENSEE NOTE 1VLOADGNDS1RLRLLOAD CIRCUIT2.5 V 0.2 VVCCINPUTSVIV 2 nstr f 2 nsVMVLOADCLRL15 pF15 pF 1 MTEST S1OPENtPLZ/tPZLtPHZ/tPZH GN
41、DVLOADV3.3 V 0.3 V3 V 2.5 ns 2.5 ns1.5 V 6 V15 pF15 pF1.8 V 0.15 VCCVCCCC2xVCC2xVCC0.15 V0.15 V0.3 V0.3 VtPLH/tPHL2xVCCVCC5 V 0.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW AND HIGH-LEVEL ENABLING1 M1 M1 M/t/2+VV +VV /2CCV
42、/2CCV /2OUTPUTCONTROLProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with in
43、ternal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristic
44、s: PRR 10 MHz, ZO= 50 . 4. The output are measured one at a time, with one transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPLHand tPHLare the same as tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 7b. Load circu
45、it and voltage waveforms. tPZLtPLZtPHZtPZHVOLVOHV0 VOUTPUTtPLHtPHLtPLHtPHLVOHOUTPUTVOLINPUTVOHVOLLOAD0 VtwtsuthDATAINPUTOUTPUTCONTROLINPUTVTIMINGINPUTOUTPUTWAVEFORM 1S1 AT VOUTPUTWAVEFORM 2S1 AT GNDSEE NOTE 2VOLLOADSEE NOTE 2IVM0 VVIVM0 VVIVM0 VVIVMVMVMVMVM0 VVIVMOHVOLTAGE WAVEFORMSPULSE DURATIONVOL
46、TAGE WAVEFORMSSETUP AND HOLD TIMESCLFROM OUTPUTUNDER TESTOPENSEE NOTE 1VLOADGNDS1RLRLLOAD CIRCUIT2.5 V 0.2 VVCCINPUTSVIV 2 nstr f 2 nsVMVLOADCLRL30 pF30 pF 1 kTEST S1OPENtPLZ/tPZLtPHZ/tPZH GNDVLOADV3.3 V 0.3 V3 V 2.5 ns 2.5 ns1.5 V 6 V50 pF50 pF1.8 V 0.15 VCCVCCVCC2xVCC2xVCC0.15 V0.15 V0.3 V0.3 VtPL
47、H/tPHL2xVCCVCC5 V 0.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW AND HIGH-LEVEL ENABLING500500500/t/2+VV +V/2VCC/2VCC/2Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13605 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should inclu
