1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origi
2、nal date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, 2 AMP, FAST TRANSIENT, LOW DROPOUT VOLTAGE REGULATOR, MONOLITHIC SILICON 13-06-12 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13612 REV PAGE 1 OF 13 AMSC N/A 5962-V050-13 Provided by IHSNot
3、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2 amp, fast transient, low dropout v
4、oltage regulator microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engine
5、ering documentation: V62/13612 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS7A7200-EP 2 amp, fast transient, low dropout voltage regulator 1.2.2 Case outline(s). The case outline(s) a
6、re as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-220 Plastic quad leadless flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-
7、lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply v
8、oltage range: Supply voltage (IN), Power good (PG), Enable (EN) -0.3 V to +7.0 V Soft start (SS), Feedback (FB), Output voltage sense input (SNS), Regulated output (OUT) . -0.3 V to VIN+ 0.3 V 2/ 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V . -0.3 V to VOUT+ 0.3 V Current supply: OUT . Internally li
9、mited PG (sink current into integrated circuit) 5 mA maximum Junction temperature range (TJ) -40C to +150C Storage temperature range (TSTG) -40C to +150C Electrostatic discharge (ESD): 3/ Human body model (HBM) . 2 kV Charged device model (CDM) 500 V 1.4 Recommended operating conditions. 4/ Operatin
10、g free-air temperature range (TA) -40C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended o
11、perating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The absolute maximum rating is VIN+ 0.3 V or +7.0 V, whichever is smaller. 3/ ESD testing is performed according to the respective JESD22 JEDEC standard. 4/ Use o
12、f this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic
13、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 4 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 5/ JA35.7 C/W Thermal resistance, junction-to-case (top) 6/ JC(TOP)33.6 C/W Thermal r
14、esistance, junction-to-board 7/ JB15.2 C/W Characterization parameter, junction-to-top 8/ JT0.4 C/W Characterization parameter, junction-to-board 9/ JB15.4 C/W Thermal resistance, junction-to-case (bottom) 10/ JC(BOTTOM)3.8 C/W 5/ The thermal resistance, junction-to-ambient under natural convection
15、is obtained in a simulation on a JEDEC standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close des
16、cription can be found in the ANSI SEMI standard G30-88. 7/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 8/ Characterization parameter, junction-to
17、-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a
18、 real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The thermal resistance, junction-to-case (bottom) is obtained by simulating a cold plate test on the exposed thermal pad. No specific JEDEC standard test exists,
19、but a close description can be found in the ANSI SEMI standard G30-88. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 5 2. APPLICABLE DOCUMENTS AMERICAN NATI
20、ONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW
21、, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) JEDEC Solid State Technology Association EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surfac
22、e Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arling
23、ton, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.
24、2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I
25、herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in f
26、igure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 6 TABLE I. Electrical performan
27、ce characteristics. 1/ Test Symbol Conditions 2/ 3/ 4/ 5/Temperature, TADevice type Limits Unit Min Max Input voltage range VIN-40C to +125C 01 1.425 6.5 V SS pin voltage V(SS)+25C 01 0.5 typical V Output voltage range VOUTAdjustable with external feedback resistors -40C to +125C 01 0.9 5.0 V Fixed
28、with voltage setting pins 0.9 3.5 Output voltage 6/ 7/ accuracy Adjustable, 25 mA IOUT 2 A -40C to +125C 01 -2.0 +2.0 % Fixed, 25 mA IOUT 2 A -3.0 +3.0 Line regulation VO(V)IOUT= 25 mA +25C 01 0.01 typical %/V Load regulation VO(IO)25 mA IOUT 2 A +25C 01 0.1 typical %/A Dropout voltage 8/ V(DO)VOUT
29、3.3 V, IOUT= 2 A, V(FB)= GND -40C to +125C 01 180 mV 3.3 V VIT(PG), V(PG)= 6.5 V -40C to +125C 01 1 A SS pin charging current I(SS)V(SS)= GND, VIN= 3.3 V -40C to +125C 01 3.5 7.2 A Output noise voltage VnBW = 100 Hz to 100 kHz, VIN= 1.5 V, VOUT= 1.2 V, IOUT= 2 A +25C 01 40.65 typical V RMSThermal sh
30、utdown temperature TsdShutdown, temperature increasing 01 +160 typical C Reset, temperature decreasing +140 typical Operating junction temperature TJ01 -40 +125 C 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified
31、temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, 1.425 V VIN6.5
32、V, VIN VOUT(TARGET)+ 0.3 V or VIN VOUT(TARGET)+ 0.5 V. When VOUT 3.5 V, VIN (VOUT+ 0.3 V) or 1.425 V, whichever is greater; when VOUT 3.5 V, VIN (VOUT+ 0.5 V). VOUT(TARGET)is the calculated target VOUTvalue from the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V in fix
33、ed configuration, or the expected VOUTvalue set by external feedback resistors in adjustable configuration. 3/ Unless otherwise specified, OUT connected to 50 to GND. This 50 load is disconnected when the test conditions specify an IOUTvalue. 4/ Unless otherwise specified, VEN= 1.1 V, COUT= 10 F, CS
34、S= 10 nF, and CFF= 0 pF. CFFis the capacitor between FB pin and OUT. 5/ Unless otherwise specified, PG pin pulled up to VINwith 100 k, 27 k R2 33 k for adjustable configuration. R2 is the bottom side of the feedback resistor between the FB pin and OUT. 6/ When the device is connected to external fee
35、dback resistors at the FB pin, external resistor tolerances are not included. 7/ The device is not tested at VOUT= 0.9, 2.7 VIN 6.5 V, and 500 mA IOUT 2 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any applicati
36、on condition that exceeds the power dissipation limit of the package. 8/ V(DO)is not defined for output voltage settings below 1.2 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG
37、 NO. V62/13612 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 9 Case X Symbol Dimensions Inches Millimeters Min Max
38、 Min Max A 0.031 0.039 0.80 1.00 A1 0.000 0.001 0.00 0.05 A2 0.007 REF 0.20 REF b 0.009 0.014 0.23 0.38 D 0.190 0.202 4.85 5.15 e 0.025 BSC 0.65 BSC e1 0.102 BSC 2.60 BSC E 0.190 0.202 4.85 5.15 L 0.017 0.025 0.45 0.65 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for re
39、ference only. 2. The package thermal pad must be soldered to the board for thermal and mechanical performance. 3. See manufacturers datasheet for details regarding the exposed thermal pad features and dimensions. 4. Falls within reference to JEDEC MO-220. FIGURE 1. Case outline - Continued. Provided
40、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 OUT 2 SNS 3 FB 4 PG 5 50 mV 6 100 mV 7 200 mV 8 GND
41、 9 400 mV 10 800 mV 11 1.6 V 12 NC 13 SS 14 EN 15 IN 16 IN 17 IN 18 GND 19 OUT 20 OUT FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13612 R
42、EV PAGE 11 Terminal symbol Description 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V Output voltage setting pins. These pins should be connected to ground or left floating. Connecting these pins to ground increases the output voltage by the value of the pin name; multiple pins can be simultaneously c
43、onnected to GND to select the desired output voltage. Leave these pins floating (open) when not in use. See the user configurable output voltage section in the manufacturers datasheet for more details. EN Enable pin. Driving this pin to logic enables the device; driving the pin to logic low disables
44、 the device. See the enable and shutdown the device section in the manufacturers datasheet for more details. FB Output voltage feedback pin. Connected to the error amplifier. See user configurable output voltage and traditional adjustable configuration section in the manufacturers datasheet for more
45、 details. A 220 F ceramic capacitor from FB pin to OUT is highly recommended. GND Ground pin. IN Unregulated supply voltage pin. It is recommended to connect an input capacitor to this pin. See input capacitor requirements section in the manufacturers datasheet for more details. NC Not internally co
46、nnected. The NC pin is not connected to any electrical node. It is strongly recommended to connect this pin and the thermal pad to a large area ground plane. See the power dissipation section in the manufacturers datasheet for more details. OUT Regulated output pin. A 4.7 F or larger capacitance is
47、required for stability. See output capacitor requirements section in the manufacturers datasheet for more details. PG Active high power good pin. An open drain output that indicates when the output voltage reaches 90% of the target. See power good section in the manufacturers datasheet for more deta
48、ils. SNS Output voltage sense input pin. See the user configurable output voltage and traditional adjustable configuration section in the manufacturers datasheet for more details. SS Soft start pin. Leaving this pin open provides soft start of the default setting. Connecting an external capacitor between this pin and the
