1、 MILITARY SPECIFICATION MICROCIRCUIT, DIGITAL, 4096-BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON This specification is approved for use by all Departmentsand Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of t
2、his specification sheet and MIL-PRF 38535. 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, programmable read-only memory (PROM) microcircuits which employ thin film nichrome (NiCr) resistors, titanium-tungsten (TiW), or zapped vertical emitter (ZVE) as t
3、he fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifyin
4、g Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type Circuit 01 512 word/8 bits per word PROM with uncommitted collector 02 512 word/8 bits per word PROM with active pull-up and a choice third high-impe
5、dance state output 03 512 word/8 bits per word PROM with active pull-up and a third high-impedance state output 04 512 word/8 bits per word PROM with uncommitted collector 05 512 word/8 bits per word PROM with active pull-up and a third high-impedance state output 1.2.2 Device class. The device clas
6、s is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line K GDFP2-F24 or CDFP3-F24 24 Flat pack X See fi
7、gure 1 24 Flat pack Y See figure 2 20 Dual-in-line Z CQCC1-N24 24 Square leadless chip carrier Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DLA LAND AND MARITIME-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed
8、to Memorydla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at https:/assist.dla.mil AMSC N/A FSC 5962 INCH-POUND MIL-M-38510/208F 21 August 2013 SUPERSEDING MIL-M-38510/208E 12 October 2010 Inactive for new
9、 design after 24 July 1995 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F 2 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range -1.5 V dc at -10 mA to +5.5 V dc Storage temperature range -
10、65 to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction to case (JC) 1/: Cases J, K, and Y . 30C/W Case X and Z . 36 C/W Output voltage applied -0.5 V dc dc to +VCCOutput sink current 100 mA Maximum power dissipation (PD) 2/ 1.02 W Maximum, junction temperature (TJ) .
11、 +175C 1.4 Recommended operating conditions. Supply voltage . +4.5 V dc minimum to +5.5 V dc maximum Minimum high-level input voltage 2.0 V dc Maximum low-level input voltage 0.8 V dc Normalized fanout (each output) 8 mA 3/ Case operating temperature range (TC) -55 C to +125 C 2. APPLICABLE DOCUMENT
12、S 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure t
13、he completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications and Standards. The following specifications and st
14、andards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specifi
15、cation for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard for Microelectronics. MIL-STD-1835 - Interface Standard Electronic Component Case Outline (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 R
16、obbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. Unless otherwise noted herein or in the contract, in the event of a conflict between the text of this document and the references cited herein (except for related specification sheets), the text of this document takes
17、 precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Heat sinking is recommended to reduce the junction temperature. 2/ Must withstand the added PDdue to short circuit test (e.g. IOS). 3/ 16 mA for circuit F de
18、vices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F 3 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activ
19、ity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. T
20、he modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.3.1 Terminal connections. The terminal connections
21、 shall be as specified on figures 3. 3.3.2 Truth table 3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 4. When required in groups A, B, or C (see 4.4), the devices shall be programmed by the manufa
22、cturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 Programmed devices. The truth table for programmed devices shall b
23、e as specified by the altered item drawing. 3.3.3 Logic diagram. The logic diagram shall be as specified on figure 5. 3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6).
24、 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table I, and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements shall be as specif
25、ied in table II, and where applicable, the altered item drawing. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF-38535. 3.8 Processing options. Since the PROM is an unprogrammed memory capable of being programmed by either t
26、he manufacturer or the user to result in a wide variety of configurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified through group A testing as defined in 3.3.2.1, tab
27、le II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Manufacturer-programmed PROM delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the a
28、ltered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 14 (see Appendix A MIL-PRF-38535.) Provided by IHSNot for ResaleNo reproduction or networking permitted wi
29、thout license from IHS-,-,-MIL-M-38510/208F 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ Device type Limits Unit Min Max High-level output voltage VOHVCC= 4.5 V, IOH= -2 mA 02,03,05 2.4 - V Low-level output voltage VOLVCC= 4.5 V, IOL= 8 mA 3/ All - 0.5 V Input clam
30、p voltage VICVCC= 4.5 V, IIN= -10 mA, TC= 25C All - -1.5 V Maximum collector cut-off current ICEXVCC= 5.5 V, VO= 5.2 V 01,04 - 100 A High-impedance (off-state) output high current IOHZVCC= 5.5 V VO= 5.2 V 02,03,05 - 100 A High-impedance (off-state) output low current IOLZVCC= 5.5 V, VO= 0.5 V 02,03,
31、05 -100 A High-level input current IIH1VCC= 5.5 V, VIN= 5.5 V All - 50 A IIH2VCC= 5.5 V, VIN= 4.5 V, special program- ming pin All - 100 A Low-level input current IIL1VCC= 5.5 V, VIN= 0.5 V All -1.0 -250 A IIL2VCC= 5.5 V, VIN= 0.5 V, for CE3and CE401,02 -1.0 -1000 A Short circuit output current IOSV
32、CC= 5.5 V, VO= 0.0 V 4/ 02,03,05 -10 -100 mA Supply current ICCVCC= 5.5 V, VIN= 0, out- puts = open 01,02,03 - 185 mA 04,05 - 155 mA Propagation delay time, high-to-low level logic, address to output tPHL1VCC = 4.5 V and 5.5 V, CL= 30 pF (see figure 6) 01,02,03 - 90 ns 04,05 - 80 ns Propagation dela
33、y time, low-to-high level logic, address to output tPLH101,02,03 - 90 ns 04,05 - 80 ns Propagation delay time, high-to-low level logic, enable to output tPHL2VCC= 4.5 V and 5.5 V, CL= 30 pF (see figure 6) 01,02,03 - 50 ns 04,05 - 40 ns Propagation delay time, low-to-high level logic, enable to outpu
34、t tPLH201,02,03 - 50 ns 04,05 40 ns 1/ Complete terminal conditions shall be as specified on table III. 2/ For device type 03, the fusing pins FE1and FE2may be grounded or floating during operation. 3/ IOL= 16 mA for circuit F devices. 4/ Not more than one output shall be grounded at one time. Outpu
35、t shall be at high logic level prior to test. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F 5 FIGURE 1. Case outline X. Dimension Symbol Inches Millimeters Notes Min Max Min Max A .045 .090 1.14 2.29 b.015 .019 .38 .48 5 c .003 .00
36、6 .08 .15 5 D - .400 - 10.16 3 E .340 .385 8.64 9.78 E1- .400 - 10.16 3 E2.125 - 3.18 - E3.030 - .76 - 14 e .050 BSC 1.27 BSC 4, 6 k.008 .015 .20 .38 10 L .250 .370 6.35 9.40 Q .010 .040 .25 1.02 2 S1.005 - .13 - 7, 8 S2.005 - .13 - 11 30 90 30 90 12, 13 Provided by IHSNot for ResaleNo reproduction
37、or networking permitted without license from IHS-,-,-MIL-M-38510/208F 6 NOTES: 1. Index area; a notch or a pin one identification mark shall be located adjacent to pin one and shall be within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark.
38、Alternately, a tab (dimension k) may be used to identify pin one. 2. Dimension Q shall be measured at the point of exit of the lead from the body. 3. This dimension allows for off-center lid, meniscus and glass overrun. 4. The basic pin spacing is .050 (1.25 mm) between centerlines. Each pin centerl
39、ine shall be located within .005 (0.13 mm) of its exact longitudinal position relative to pins relative to pins 1 and 24. 5. All leads increase maximum limit by .003 (0.08mm) measured at the center of the flat, when lead finish A is applied. 6. Twenty-two spaces. 7. Applies to all four corners (lead
40、s number 3, 10, 15, and 22). 8. Dimension S1may be .000 (0.00 mm) if leads number 3, 10, 15, and 22 bend toward the cavity of the package within one lead width from the point of entry of the lead, into the body or if the leads are brazed to the metallized ceramic body (see MIL-STD-1835) . 9. Optiona
41、l configuration: if this configuration is used, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 10. Optional, see note 1. If a pin one identification mark is used in addition to this tab, the minimum limit of dimension k does not apply. 11. Applies
42、to leads number 2, 11, 14, and 23. 12. Lead configuration is optional within dimension E except dimensions b and c apply (see MIL-STD-1835). 13. Applies to lead numbers 1, 2, 11, 12, 13, 14, 23, and 24. 14. Applies to all edges. FIGURE 1. Case outline X Continued. Provided by IHSNot for ResaleNo rep
43、roduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F 7 FIGURE 2. Case outline Y. Dimension Symbol Inches Millimeters Notes Min Max Min Max A - .175 - 4.44 b .016 .020 .41 .51 11, 8 b1.040 .060 1.02 1.52 8, 2 C .008 .012 .20 .30 11, 8 D .970 1.010 24.64 25.65 4 E .280 .300
44、7.11 7.62 4 E1.290 .320 7.37 8.13 7 e .090 .110 2.29 2.79 5, 9 L .125 .180 3.18 4.58 L1.150 - 3.81 - Q .020 .060 .51 1.52 3 S - .098 - 2.49 6 S1.005 - .13 - 6 S2.005 - .13 - 8 0 15 0 15 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F
45、 8 NOTES: 1. Index area; a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. 2. The minimum limit for dimension b1may be .020 (.51 mm) for
46、 leads number 1, 10, 11, and 20 only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54 mm) between centerlines. Each pin centerline shall be located within .010 (
47、.25 mm) of its exact longitudinal position relative to pins 1 and 20. 6. Applies to all four corners (leads number 1, 10, 11, and 20) (see MIL-STD-1835). 7. Lead center when is 0. E1shall be measured at the centerline of leads (see MIL-STD-1835). 8. All leads Increase maximum limit by .003 (.08 mm)
48、measured at the center of the flat, when lead finish A is applied. 9. Eighteen spaces. 10. No organic or polymeric materials shall be molded to the bottom of the package. 11. Applies to all leads. FIGURE 2. Case outline Y Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/208F 9 Device type 01 and 02 03 04 and 05 Case outline J, K, X, and Z J, K, and X Y
