1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET 35 36 37 38 REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia D
2、EFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Robert M. Heber DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 07-04-25 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ALTERABLE (IN-SYS
3、TEM REPROGRAMMABLE), 3M GATES, PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-02530 SHEET 1 OF 38 DSCC FORM 2233 APR 97 5962-E317-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC
4、UIT DRAWING SIZE A 5962-02530 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting high reliability (device classes Q and M) and space application (device class V
5、. A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 02530 01 Q Z C Federal
6、RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked
7、 with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows
8、: Device type Generic number Circuit function Access time 01 XQ(R)2V3000-4 3M gate programmable array 0.44 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self
9、-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline
10、letter Descriptive designator Terminals Package style Z See figure 1 717 Ceramic column grid array CCGA (Reference JEDEC MO-128) 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for Resa
11、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02530 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range to ground potential (V
12、CCINT) - - -0.5 V dc to +1.65 V dc Auxiliary supply voltage range to ground potential (VCCAUX) - -0.5 V dc to +4.0 V dc Output drivers supply voltage range to ground potential (VCCO) - -0.5 V dc to +4.0 V dc Key memory battery backup supply voltage range to ground potential (VBATT) - - -0.5 V dc to
13、+4.0 V dc DC input voltage range (user and dedicated I/Os ( VIN) 3/ - - -0.5 V to VCCO + 0.5V DC input voltage range (VREF) using Ref - - -0.5 V to VCCO + 0.5V Voltage applied to three-state output(VTS) - - -0.5 V to 4.0V Lead temperature (soldering, 10 seconds) - - +220C Power dissipation (PD) - -
14、2.0 W Thermal resistance, junction-to-case (JC): Case outlines Z- - 4.2C/W 4/ Junction temperature (TJ) for ceramic packages- - +145C 5/ Storage temperature range - - -65C to +150C 1.4 Recommended operating conditions. Supply voltage relative to ground(VCCINT) - - +1.425 V dc minimum to +1.575 V dc
15、maximum Supply voltage relative to ground(VCCAUX) - - +3.0 V dc minimum to +3.6 V dc maximum Supply voltage relative to ground(VCCO) - - +1.2 V dc minimum to +3.6 V dc maximum Supply voltage relative to ground(VBATT) - - +1.0 V dc minimum to +3.6 V dc maximum Data retention VCCINTvoltage (VDRINT) -
16、- +1.2 V minimum Data retention VCCAUXvoltage (VDRI)- - +2.5 V minimum VREFcurrent per bank IREF- -10 A Input leakage current IL- -10 A Pad pull-up (when selected) VIN= 0 V, VCCO = 3.3 V (sample tested) IRPU6/ - - 250 A Pad pull-down (when selected) VIN= 3.6 V (sample tested) IRPD6/ - - 250 A Batter
17、y supply current IBATT- - 100 nA Quiescent VCCINTsupply current (ICCINTQ) Typical 0.2 A - - 1.30 A maximum Quiescent VCCOsupply current 7/ 8/ (ICCOQ) Typical 2.0 mA - - 6.25 mA maximum Quiescent VCCAUXsupply current 7/ 8/ (ICCAUXQ) Typical 20 mA- 95 mA maximum Input high voltage ( VIH)- - 2.0 V dc m
18、inimum Input low voltage (VIL) - - 0.8 V dc maximum Maximum input signal transition time (tIN)- - 250 ns Case operating temperature range (TC) - - -55C to +125C 1.5 Radiation features. (RHA marked devices only) Maximum total dose available (dose rate = 50 300 rads(Si)/s) .200K rads(Si) 1/ All voltag
19、e values in this drawing are with respect to VSS2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Inputs configured as PCI are fully PCI compliant. This statement takes p
20、recedence over any specification that would imply that the device is not PCI compliant. 4/ When a thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 5/ Maximum junction temperature shall not be exceeded except for allowable short dur
21、ation burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circu
22、its. 7/ With no output current loads and no active input pull-up resistors. All I/O pins are 3-stated and floating. 8/ Data are retained even if VCCOdrops to 0 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59
23、62-02530 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified her
24、ein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microc
25、ircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearc
26、h/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issu
27、es of these documents are those cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192M-95 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM public
28、ations should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. JEDEC Publication EIA/JEP 95 - Registered and Standard Outlines for Semiconductor Devices (
29、Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be ava
30、ilable in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulati
31、ons unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modific
32、ation in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions
33、. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. Provided by I
34、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02530 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 3.2.2 Terminal connections. The terminal connections shall be as
35、specified on figure 2. 3.2.3 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and posti
36、rradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics are the preirradiation and postirradiation parameter limits as specified in table IA and shall apply over the full case operating or junction temperature range as applicable. 3.4 Electrical tes
37、t requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages
38、 where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with
39、MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as requi
40、red in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance s
41、hall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for d
42、evice classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-3
43、8535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that aff
44、ects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of t
45、he reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For
