1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added new note 5 to section 1.3, renumbered remaining notes. Deleted the designation for case outline Z in section 1.3, Z was a typo. Added note to end of section 1.6.3, and updated the figure in Table I note 10. ksr 07-04-23 Robert M. Heber B Ad
2、d device types 05 through 08 to section 1.2.2; add and edit footnote designations in section 1.2.2 and the corresponding footnotes at bottom of page 2. Made additional changes in paragraphs for inclusion of devices 05 through 08 where applicable. Added new test in 4.4.1.f.(4) for thermal runaway. Ma
3、de changes to Table I where applicable, also corrected figure in footnote 6/ of Table I. ksr 08-03-11 Robert M. Heber C Add case outlines Z and U; modify needed paragraphs to accommodate the addition of the case outlines. Make changes to Table I; clarifications for 5 V tolerance, standby currents, a
4、nd I/O related changes. Modified footnote 3/ for Table IIB. ksr 09-08-17 Charles F. Saffle D Updated devices for class V. Updated footnote information for 1.2.2. Updated 2.2. Added and resequenced footnotes in Table I. Added binning circuit delay test in Table I. Deleted “and Table IIA note 8/ herei
5、n” from Table I footnote 1/. Deleted “Qualification inspection for all devices (01 to 08) complies with class Q level requirements only.” from 4.3. Updated 4.4.2.2. Updated Table IIA and footnotes. Updated Table IIB. Removed vendor website URL from 6.7. Updated boilerplate to current requirements. l
6、hl 12-03-09 Charles F. Saffle E Updated 4.6 to boilerplate requirement which removed reference to vendor brand software. Updated boilerplate to current requirements. lhl 12-06-20 Charles F. Saffle REV E E E E E E SHEET 35 36 37 38 39 40 REV E E E E E E E E E E E E E E E E E E E E SHEET 15 16 17 18 1
7、9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Raje
8、sh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 250,000 GATES, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 06-04-20 AMSC N/A REVISION LEVEL E SIZE A
9、CAGE CODE 67268 5962-04219 SHEET 1 OF 40 DSCC FORM 2233 APR 97 5962-E252-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC
10、FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number
11、 (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 04219 01 Q X C | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finis
12、h designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices mee
13、t the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 RTAX250S 250,000 gate fiel
14、d programmable gate array 02 RTAX250S-1 250,000 gate field programmable gate array 1/ 03 RTAX250S 250,000 gate field programmable gate array 2/ 04 RTAX250S-1 250,000 gate field programmable gate array 1/ 3/ 05 RTAX250SL 250,000 gate field programmable gate array 4/ 06 RTAX250SL-1 250,000 gate field
15、programmable gate array 1/ 4/ 07 RTAX250SL 250,000 gate field programmable gate array 4/ 5/ 08 RTAX250SL-1 250,000 gate field programmable gate array 1/ 4/ 6/ Note: These devices are specified at junction operating temperature and not at case operating temperature. 1.2.3 Device class designator. The
16、 device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q
17、 or V Certification and qualification to MIL-PRF-38535 1/ Timing performance of the RTAX250S-1 and RTAX250SL-1 devices shall be approximately 15% faster than the RTAX250S and RTAX250SL devices respectively (End users may select the appropriate device speed grade through timing calculations based on
18、timing simulation of specific designs with manufacturers Libero/Designer software, see 6.7 herein). 2/ Device type 03 is device type 01 with additional testing (see 4.2.2.f). Device type 03 is only offered as a Class Q device. 3/ Device type 04 is device type 02 with additional testing (see 4.2.2.f)
19、. Device type 04 is only offered as a Class Q device. 4/ Silicon used for all devices are the same silicon, at 125C final electrical test, device type 05 to 08 is screened to a lower ICCA limit (see Table I herein). 5/ Device type 07 is device type 05 with additional testing (see 4.2.2.f). Device ty
20、pe 07 is only offered as a Class Q device. 6/ Device type 08 is device type 06 with additional testing (see 4.2.2.f). Device type 08 is only offered as a Class Q device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI
21、ZE A 5962-04219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 352 Ceramic Quad Fl
22、at Pack Y See figure 1 208 Ceramic Quad Flat Pack Z See figure 1 624 Ceramic Land Grid Array (LGA) U See figure 1 624 Ceramic Column Grid Array (CGA) 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Ab
23、solute maximum ratings (for 1.5V/1.8V/2.5V/3.3V operating conditions). 7/ DC core supply voltage (VCCA) -0.3 to +1.7 V DC I/O supply voltage (VCCI) . -0.3 to +3.75 V DC supply voltage for differential I/Os (VCCDA) . -0.3 to +3.75 V DC I/O reference voltage (VREF) -0.3 to +3.75 V DC external pump sup
24、ply voltage (VPUMP) -0.3 to +3.75 V Input voltage (VI) -0.5 to +4.1 V 8/ Output voltage (VO) -0.5 to +3.75 V Storage temperature range (VSTG) -65oC to +150oC Lead temperature (soldering, 10 seconds) X and Y 300oC Z and U . 245 oC Maximum junction temperature (TJ) . 135oC 9/ Thermal resistance, junct
25、ion-to-case (JC): Case outline X . 0.7oC/W 10/ 13/ Case outlines Y 0.8oC/W 10/ 13/ Case outlines Z and U . 3.8 oC/W 11/ 13/ Thermal resistance, junction-to-board (JB) for case outline U . 4.6 oC/W 12/ 13/ AC core supply transient voltage (VCCA) . -0.3 to +1.8 V 14/ 7/ Stresses above the absolute max
26、imum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 8/ Overshoot/Undershoot limits: For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer than 10% of the period or 11 ns wh
27、ichever is smaller. Current during the transition must not exceed 95 mA. For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period or 11 ns whichever is smaller. Current during the transition must not exceed 95 mA. Note: This specification
28、 does not apply to the PCI standard. The PCI I/Os of this device are compliant to the PCI standard including the PCI overshoot/undershoot specifications. 9/ Maximum junction temperature shall not be exceeded except for allowable short durations during burn-in screening conditions in accordance with
29、method 5004 of MIL-STD-883. TJ = 135 oC applies with wafer lot numbers starting with D2xxxx. For older wafer lot numbers starting with D1xxxx, the TJ = 125 oC still applies. 10/ JC for case outlines X and Y refers to the thermal resistance between the junction and the bottom of the package. 11/ JC f
30、or case outlines Z and U refers to the thermal resistance between the junction and the top of the package (surface of the metal lid). 12/ JB for case outline U refers to the thermal resistance between the junction and the tips of the solder columns (where the device is attached to the circuit board)
31、. 13/ All thermal resistance data are obtained through simulation with computational fluid dynamic software. For case outlines Z and U, the JB is simulated with 4L/2P SMT board per JEDEC Standard No. 51. 14/ AC transient VCCA limit is for radiation induced transients less than 10s duration, and not
32、intended for repetitive use. Core voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the transient does not exceed 1.8 V at any time, and the total time that the transient exceeds 1.575 V does not exceed 10 s in du
33、ration. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 1.5V core sup
34、ply voltage . 1.425 to 1.575 V dc 1.5V I/O supply voltage . 1.425 to 1.575 V dc 1.8V I/O supply voltage . 1.71 to 1.89 V dc 2.5V I/O supply voltage . 2.375 to 2.625 V dc 3.3V I/O supply voltage . 3.0 to 3.6 V dc 2.5V VCCDA I/O supply voltage (no differential I/O used) . 2.375 to 2.625 V dc 3.3V VCCD
35、A I/O supply voltage (differential or voltage referenced I/O used) . 3.0 to 3.6 V dc 3.3V VPUMP supply voltage range 3.0 to 3.6 V dc Junction operating temperature range (TJ) . -55oC to +125oC 1.5 Power-Up/Down Sequence. All device I/Os are tri-stated during power-up until normal device operating co
36、nditions are reached, which is when I/Os enter user mode. VCCA, VCCI, and VCCDA can be powered up or powered down in any sequence. All device I/Os are hot-swap compliant with cold-sparing support (except PCI). 1.5.1 R-cells and I/O Registers. On a chip-wide basis at power-up, all R-cells and I/O Reg
37、isters are either cleared or preset by driving the global clear (GCLR) and global preset (GPSET) inputs (see Figure 3). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. 1.6 Device Logic Configuration. 1.6.1 Core array logics include two types of logic modules: th
38、e register cell (R-cell) and the combinatorial cell (C-cell). C-cell contains carry logic for efficient arithmetic functions. R-cell appears as a single D-type flip-flop to user, but is implemented in silicon with triple module redundancy (TMR) to improve SEU performance. Each TMR R-cell consists of
39、 three master-slave latch pairs, each with asynchronous self-correcting feedback paths. Output of the TMR R-cell is the result of the majority voting of the outputs of the three flip flops in the TMR R-cells. Logic modules are grouped as SuperCluster, each SuperCluster has two Clusters, and each Clu
40、ster includes two C-cells, one R-cell, two transmit (TX) and two receive (RX) routing buffers. Each SuperCluster also includes an independent buffer module. On the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. There are four core tiles in this
41、device and each tile has 176 SuperClusters, resulting in a total of 1,408 R-cells and 2,816 C-cells in the device. 1.6.2 Clock Resources are available with two types of global clock networks throughout the chip. There are four dedicated hardwired clock input pins (HCLKA/B/C/D) that will directly dri
42、ve all the sequential modules (R-cells, I/O registers, embedded RAM/FIFO). There are also four global clock input pins (CLKE/F/G/H) for routed clock distribution networks that are buffered prior to clocking the R-cells; the routed clocks can also be programmed to drive S0, S1, PSET, and CLR of a reg
43、ister, or as the inputs of any C-cell. Input levels for all clocks are compatible with all supported I/O standards (there is a P/N pin pair to support differential I/O standards). All clock networks have been hardened to improve SEU performance. 1.6.3 Embedded RAM is available as a global resource.
44、There are three 4,608-bit RAM blocks in each tile, with a total of 55,296 bits in the device. Each 4,608-bit RAM block can be organized as 128x36, 256x18, 512x9, 1,024x4, 2,048x2, or 4,096 x1 (Depth x Word in bits), and are cascadable to create larger memory sizes. Each RAM block has independent rea
45、d and write ports, which enables simultaneous read and write operations; it also contains its own embedded FIFO controller, allowing the RAM blocks to be configured as either RAM or FIFO. SRAM structures are susceptible to radiation upsets, to achieve high level SEU performance; manufacturer has pro
46、vided an IP core to enhance the SEU tolerance of the embedded RAM blocks by mitigating upsets with Error Detection and Correction (EDAC) and background memory-refresher (or scrubber). Registers in the FIFO controller are not hardened for radiation, so when high SEU tolerance is required, the FIFO co
47、ntrol unit should be implemented with core logic. Note: Simultaneous read and write operations to the same address is not supported. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04219 DLA LAND AND MARITIME
48、 COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 1.6.4 Multi-Standard I/Os are available on all I/O pins. Below table shows all supported I/O standards. Each I/O provides programmable slew rates, drive strength, and weak pull-up and pull-down circuits (in the order of 10k),
49、it also includes three registers (input (InReg), output (OutReg), and enable (EnReg). I/Os are organized into eight banks (0-7) with two banks per device side. Each I/O bank has a common VCCI and a common reference-voltage bus. For each I/O bank, multiple I/O standards may be selected, however, all I/O sta
