DLA SMD-5962-04219 REV E-2012 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 250 000 GATES MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added new note 5 to section 1.3, renumbered remaining notes. Deleted the designation for case outline Z in section 1.3, Z was a typo. Added note to end of section 1.6.3, and updated the figure in Table I note 10. ksr 07-04-23 Robert M. Heber B Ad
2、d device types 05 through 08 to section 1.2.2; add and edit footnote designations in section 1.2.2 and the corresponding footnotes at bottom of page 2. Made additional changes in paragraphs for inclusion of devices 05 through 08 where applicable. Added new test in 4.4.1.f.(4) for thermal runaway. Ma
3、de changes to Table I where applicable, also corrected figure in footnote 6/ of Table I. ksr 08-03-11 Robert M. Heber C Add case outlines Z and U; modify needed paragraphs to accommodate the addition of the case outlines. Make changes to Table I; clarifications for 5 V tolerance, standby currents, a
4、nd I/O related changes. Modified footnote 3/ for Table IIB. ksr 09-08-17 Charles F. Saffle D Updated devices for class V. Updated footnote information for 1.2.2. Updated 2.2. Added and resequenced footnotes in Table I. Added binning circuit delay test in Table I. Deleted “and Table IIA note 8/ herei
5、n” from Table I footnote 1/. Deleted “Qualification inspection for all devices (01 to 08) complies with class Q level requirements only.” from 4.3. Updated 4.4.2.2. Updated Table IIA and footnotes. Updated Table IIB. Removed vendor website URL from 6.7. Updated boilerplate to current requirements. l
6、hl 12-03-09 Charles F. Saffle E Updated 4.6 to boilerplate requirement which removed reference to vendor brand software. Updated boilerplate to current requirements. lhl 12-06-20 Charles F. Saffle REV E E E E E E SHEET 35 36 37 38 39 40 REV E E E E E E E E E E E E E E E E E E E E SHEET 15 16 17 18 1
7、9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Raje
8、sh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 250,000 GATES, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 06-04-20 AMSC N/A REVISION LEVEL E SIZE A
9、CAGE CODE 67268 5962-04219 SHEET 1 OF 40 DSCC FORM 2233 APR 97 5962-E252-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC
10、FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number
11、 (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 04219 01 Q X C | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finis
12、h designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices mee
13、t the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 RTAX250S 250,000 gate fiel
14、d programmable gate array 02 RTAX250S-1 250,000 gate field programmable gate array 1/ 03 RTAX250S 250,000 gate field programmable gate array 2/ 04 RTAX250S-1 250,000 gate field programmable gate array 1/ 3/ 05 RTAX250SL 250,000 gate field programmable gate array 4/ 06 RTAX250SL-1 250,000 gate field
15、programmable gate array 1/ 4/ 07 RTAX250SL 250,000 gate field programmable gate array 4/ 5/ 08 RTAX250SL-1 250,000 gate field programmable gate array 1/ 4/ 6/ Note: These devices are specified at junction operating temperature and not at case operating temperature. 1.2.3 Device class designator. The
16、 device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q
17、 or V Certification and qualification to MIL-PRF-38535 1/ Timing performance of the RTAX250S-1 and RTAX250SL-1 devices shall be approximately 15% faster than the RTAX250S and RTAX250SL devices respectively (End users may select the appropriate device speed grade through timing calculations based on
18、timing simulation of specific designs with manufacturers Libero/Designer software, see 6.7 herein). 2/ Device type 03 is device type 01 with additional testing (see 4.2.2.f). Device type 03 is only offered as a Class Q device. 3/ Device type 04 is device type 02 with additional testing (see 4.2.2.f)
19、. Device type 04 is only offered as a Class Q device. 4/ Silicon used for all devices are the same silicon, at 125C final electrical test, device type 05 to 08 is screened to a lower ICCA limit (see Table I herein). 5/ Device type 07 is device type 05 with additional testing (see 4.2.2.f). Device ty
20、pe 07 is only offered as a Class Q device. 6/ Device type 08 is device type 06 with additional testing (see 4.2.2.f). Device type 08 is only offered as a Class Q device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI
21、ZE A 5962-04219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 352 Ceramic Quad Fl
22、at Pack Y See figure 1 208 Ceramic Quad Flat Pack Z See figure 1 624 Ceramic Land Grid Array (LGA) U See figure 1 624 Ceramic Column Grid Array (CGA) 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Ab
23、solute maximum ratings (for 1.5V/1.8V/2.5V/3.3V operating conditions). 7/ DC core supply voltage (VCCA) -0.3 to +1.7 V DC I/O supply voltage (VCCI) . -0.3 to +3.75 V DC supply voltage for differential I/Os (VCCDA) . -0.3 to +3.75 V DC I/O reference voltage (VREF) -0.3 to +3.75 V DC external pump sup
24、ply voltage (VPUMP) -0.3 to +3.75 V Input voltage (VI) -0.5 to +4.1 V 8/ Output voltage (VO) -0.5 to +3.75 V Storage temperature range (VSTG) -65oC to +150oC Lead temperature (soldering, 10 seconds) X and Y 300oC Z and U . 245 oC Maximum junction temperature (TJ) . 135oC 9/ Thermal resistance, junct
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