1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Technical change for IDDQtest in table IA. - LTG 07-04-17 Thomas M. Hess B Change measurements, in case outline X in figure 1. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-01-27 Thomas M. Hess C Add subgroups
2、to table IIA in groups C and D. - LTG 11-06-23 David J. Corbett D To correct switching waveforms input/output test limits to figure 4. Add test equivalent circuits and footnote 1 to figure 4. Delete class M requirements throughout.MAA 13-01-25 Thomas M. Hess REV SHEET REV D D SHEET 15 16 REV STATUS
3、REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF T
4、HE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, RADIATION HARDENED, ADVANCED CMOS, 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT, WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 06-12-21 REVISION LEVEL D SIZ
5、E A CAGE CODE 67268 5962-06239 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E182-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 D
6、SCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PI
7、N). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 06239 01 V X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see
8、1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s
9、) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACS630 16-bit parallel error detection and correction circuit with three-state outputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
10、 follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 28 Flat pack 1.2.
11、5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL
12、 D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +6.0 V dc Voltage on any pin during operation (VI/O) -0.3 V dc to VDD+ 0.3 V dc DC input current (IIN) 10 mA Storage temperature range (TSTG) -65C to +150C Maximum junction temperature (TJ
13、) . +175C Thermal resistance junction-to-case (JC) 20C/W Maximum power dissipation (PD) . 350 mW 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Input voltage on any pin (VIN) . 0.0 V dc to VDDCase operating temperature range (TC) . -55C to +125C Maximum
14、 input rise or fall time (tr, tf) 20 ns 1.5 Radiation features. Maximum total dose available (dose rate = 50 to 300 rad(Si)/s) 1.0 x 105rads (Si) Single event phenomenon (SEP): No SEL occurs at effective LET (see 4.4.4.5) 108 MeV-mg/cm24 No SEU occurs at effective LET (see 4.4.4.5) 108 MeV- mg/cm24/
15、 Neutron fluence 1X 1014n/cm24/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited
16、in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
17、DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D
18、, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to VSS. 3/ The limits for the
19、parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise specified. 4/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided
20、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a pa
21、rt of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of
22、 semiconductor Devices. (Copies of these documents are available online at http:/www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references
23、cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accorda
24、nce with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and ph
25、ysical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Function tables. T
26、he function tables shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revisi
27、on level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are a
28、s specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be mar
29、ked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option,
30、 the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For dev
31、ice classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for
32、this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircu
33、its delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical perform
34、ance characteristics. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VDD +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level input voltage 2/ VIH1, 2, 3 All 0.7VDDV Low level input voltage 2/ VIL1, 2, 3 All 0.3VDDV Positive input clamp voltage VIC+ For
35、 input under test IIN= 18 mA, VDD= 0.0 V 1, 2, 3 All 0.4 1.5 V Negative input clamp voltage VIC- For input under test IIN= -18 mA, VDD= open 1, 2, 3 All -1.5 -0.4 V High level output voltage (except DEF and SEF) VOH1IOH= -16 mA 1, 2, 3 All VDD 0.8 V V IOH= -100 A VIN= 0.7VDDor 0.3VDDVDD= 4.5 V to 5.
36、5 V VDD 0.2 V High level output voltage (DEF and SEF only) VOH2IOH= -8 mA 1, 2, 3 All VDD 0.8 V V IOH= -100 A VIN= 0.7VDDor 0.3VDDVDD= 4.5 V to 5.5 V VDD 0.2 V Low level output voltage (except DEF and SEF) VOL1IOL= 16 mA 1, 2, 3 All 0.4 V IOL= 100 A VIN= 0.7VDDor 0.3VDDVDD= 4.5 V to 5.5 V 0.2 Low le
37、vel output voltage (DEF and SEF only) VOL2IOL= 8 mA 1, 2, 3 All 0.4 V IOL= 100 A VIN= 0.7VDDor 0.3VDDVDD= 4.5 V to 5.5 V 0.2 Three-state output leakage current IOZVDD= 4.5 V to 5.5 V VIN= VDDor VSS1, 2, 3 All -10 10 A Input leakage current IINVDD= 4.5 V to 5.5 V VIN= VDDor VSS1, 2, 3 All -5 +5 A Sho
38、rt circuit output current 3/ 4/ IOSVOUT= VDDor VSS1, 2, 3 All -300 300 mA Power dissipation 5/ 6/ 7/ PDCL= 20 pF 1, 2, 3 All 400 W/ MHz Quiescent supply current IDDQVIN= VDDor VSSVDD= 5.5 V 1, 2, 3 All 100 A M, D, P, L, R 1 All 100 VDDsupply current, operating IDD (OP)VIH= 5.0 V, CL= 20 pF VIL= 0.0
39、V, VDD= 5.0 V 1, 2, 3 All 2.0 mA/ MHz Input capacitance CINf = 1 MHz at 0 V See 4.4.1c 4 All 24 pF Output capacitance COUTf = 1 MHz at 0 V See 4.4.1c 4 All 24 pF Functional tests See 4.4.1d 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted w
40、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VDD +5.5 V unless
41、 otherwise specified Group A subgroups Device type Limits Unit Min Max Propagation delay time, DBn to CBn tPLH1, tPHL1 VDD= 5.0 V 10% VSS= 0 V See figure 4 9, 10, 11 All 5.5 11.0 ns Propagation delay time, S1 to DEF tPLH29, 10, 11 All 3.0 8.0 ns Propagation delay time, S1 to SEF tPLH39, 10, 11 All 3
42、.0 8.0 ns Propagation delay time, output enable, S0 to DBn or CBn tPZH, tPZL9, 10, 11 All 2.0 9.5 ns Propagation delay time, output disable, S0 to DBn or CBn tPHZ, tPLZ9, 10, 11 All 3.5 8.0 ns Setup time, high or low, DBn or CBn to S1 ts9, 10, 11 All 0.5 ns Hold time, high or low, DBn or CBn to S1 t
43、h9, 10, 11 All 3.5 ns 1/ Devices supplied to this drawing are characterized at all levels M, D, P, L, and R of irradiation. However, this device is only tested at the R level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation elect
44、rical measurements for any RHA level, TA= +25C. 2/ Functional tests are conducted in accordance with the MIL-STD-883 with the following input test conditions: VIH= VIH(min) +20%, -0%; VIL= VIL(max) +0%, -50%; as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested usi
45、ng any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3/ Not more than one output may be shorted at a time for a maximum duration of one second. 4/ Supplied as a design limit, but not guaranteed or tested. 5/ Guaranteed by characterization, but not teste
46、d. 6/ Power does not include power contribution of any CMOS output sink current. 7/ Power dissipation specified per switching output. TABLE IB. SEP test limits . 1/ 2/ 3/ Device type Bias VDD= 4.5 V For SEU test Bias VDD= 5.5 V For SEL test Effective LET no SEU occurs MeV/(mg/cm2) Effective LET No S
47、EL occurs MeV/(mg/cm2) All LET 108 LET 108 1/ Devices that contain cross coupled resistance must be tested at the maximum rated TA. For SEP test conditions, see 4.4.4.5 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testi
48、ng. Test plan must be approved by TRB and qualifying activity. 3/ Worst case temperature for latch-up test TA= +125C 10C. Test temperature for SEU test TA= +25C 10C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06239 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Case outline X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted w
