1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Muhammad A. Akbar DLA LAND AND MARITIME COLU
2、MBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Muhammad A. Akbar THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, CMOS, RADIATION HARDENED, CLOCK NETWORK MANAGER, MONOLITHIC SILICON AND AGENCIES O
3、F THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 2012-09-04 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-08243 SHEET 1 OF 47 DSCC FORM 2233 APR 97 5962-E442-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
4、 A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and space application (device class V). A choice of case outlines an
5、d lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 08243 01 Q X X Federal stock class designator RHA desi
6、gnator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desig
7、nator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 UT7R2XLR816 Radiation hardened clock network manager 02 UT7R2XLR816 Radiation hardened clock network manager 1/ 1.2.3 Device
8、 class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 an
9、d as follows: Outline letter Descriptive designator Terminals Package style X See figure 1. 168 Ceramic land grid array (CLGA) 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. _ 1/ Device type 02 provides a QML class Q product with the additional testin
10、g as specified in paragraph 4.2.1.d herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maxi
11、mum ratings. 1/ 2/ Core and analog power supply voltage range (VDD_C and VDD_A) 3/ . -0.3 V dc to 4.0 V dc Output bank power supply voltage range (VDD_0Qthrough VDD_7Q) -0.3 V dc to 4.0 V dc Voltage on any core input pin (VIN_C) -0.3 V to VDD_C+ 0.3 V Voltage on any reference input pin (VIN_R) . -0.
12、3 V to VDD_C+ 0.3 V Voltage on any FB_IN input pin (VIN_FB) . -0.3 V to VDD_C+ 0.3 V Voltage on any clock bank output (VOUT_LVCMOS) -0.3 V to VDD_nQ+ 0.3 V Voltage on any clock bank output (VOUT_LVDS) -0.3 V to VDD_nQ+ 0.3 V Voltage on XTAL2, FB_OUT and LOCK outputs (VO) -0.3 V to VDD_C+ 0.3 V DC in
13、put current (II) 10 mA Maximum power dissipation (PD) permitted at TC = 125C . 5.0 W 4/ Storage temperature range (TSTG) -65C to +150C Maximum junction temperature (TJ) . +150C 5/ Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC). 5 C/W Electrostatic discharg
14、e (ESD) protection (human body model) (ESDHBM) 750 V 1.4 Recommended operating conditions. Core and Analog power supply voltage range (VDD_Aand VDD_C,) 3.0 V dc to 3.6 V dc Output bank operating voltage range (VDD_0Qthrough VDD_7Q) 2.25 V dc to 3.6 V dc 6/ Voltage on any configuration and control in
15、put pin (VIN_CONTROL) . 0 V to VDD_C V Voltage on reference input pin (VIN_REF) . 0 V to VDD_C V Voltage on XTAL_IN input pin (VIN_XTAL) 0 V to VDD_C V Maximum Voltage on LVDS input (VIN_LVDIN) 2.4 V Voltage on FB_IN input pin (VIN_FB) 0 V to VDD_C V Voltage on LOCK output (VOUT_LOCK) 0 V to VDD_C V
16、 Voltage on XTAL_OUT output (VOUT_XTAL) . 0 V to VDD_C V Voltage on any LVCMOS clock bank output (VOUT_nQ) . 0 V to VDD_nQ V Voltage on any LVDS clock bank output (VOUT_LVDS) 0.925 V to 1.65V Voltage on FB_OUT output (VOUT_FB) . 0 V to VDD_C V Case operating temperature range (TC) . -55C to +125C 1.
17、5 Radiation features. Maximum total dose available (dose rate = 50 300 rad (Si)/s) 100 krad (Si) No Single event latchup (SEL) occurs at effective LET (see 4.4.4.3.) 109 MeV-cm2/mg 7/ 8/ No Onset single event upset (SEU) at effective LET (see 4.4.4.3). 109 MeV-cm2/mg 8/ 9/ Neutron fluence 1.0 X 1014
18、n/cm27/ _ 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Expo
19、sure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2/ All voltages are referenced to VSS, or ground. 3/ References to power supply VDD_A/C indicate both core power supply VDD_C and analog power supply VDD_A. 4/ Maximum power dissipation (PD
20、) shall be measured per MIL-STD-883, method 1012, paragraph 3.4.1, PD= (TJ max - TC max) / JC. 5/ Maximum junction temperature may be increased to +175C during burn-in and steady-state life testing. 6/ When configuring an output bank for LVDS drive, the corresponding VDD_nQrange is 3.0 V to 3.6 V. 7
21、/ Worst case temperature and voltage of TC= +125C 10C, VDD_Aand VDD_C= 3.6 V, and VDD_nQ= 3.6 V for SEL. 8/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. 9/ Worst case temperature and voltage of TC= +25C
22、 10C, VDD_A, and VDD_C= 3.0 V, and VDD_nQ= 3.0 V for SEU. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2.
23、APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DE
24、PARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-
25、HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2
26、Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 -Standard Guide for
27、the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices (Copies of these documents are available online at http:/www.astm.org/ or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) 2.3 Order of precedenc
28、e. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirement
29、s. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3
30、.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections.
31、 The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on figures 4a through figures 4f Provide
32、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 3.2.5 Radiation exposure circuit. The radiation exposure circuit sha
33、ll be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance
34、 characteristics and post-irradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup
35、 are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking t
36、he “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as requi
37、red in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Marit
38、ime -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein . 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V
39、in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVE
40、L SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C +3.0 V (VDD_A/C) +3.6 V unless otherwise specified Group A subgroups Device type Limits 2/ Unit Min Max DC Electrical Characteristics 3-level and LVCMOS/LVTTL inputs High-level i
41、nput voltage (REF, FB_IN and sOE ) VIH1, 2, 3 All +2.0 V Low-level input voltage (REF, FB_IN and sOE ) VIL1, 2, 3 All +0.8 V High-level input voltage VIHH3/ Ternary inputs 1, 2, 3 All (VDD_C 0.6) V Mid-level input voltage VIMM3/ 1, 2, 3 All (VDD_C/2) 0.3 (VDD_C/2) + 0.3 V Low-level input voltage VIL
42、L3/ 1, 2, 3 All +0.6 V Positive input clamp voltage (except REF and FB_IN pin) VIC+For input under test: IIN = +18 mA; VDD_A/C = 0.0 V 1, 2, 3 All +0.4 +1.5 V Negative input clamp voltage (all inputs) VIC-For input under test: IIN = -18 mA; VDD_A/C = 0.0 V 1, 2, 3 All -1.5 -0.4 V Input cold spare le
43、akage current (REF, FB_IN) ICSFor input under test: VIN= +3.6 V; VDD_C= 0.0 V 0.3 V 1, 2, 3 All -5 +5 A Input leakage current on 2-level inputs IIL-2LFor input under test: VIN= +3.6 V or 0.0 V; VDD_A/C= +3.6 V Pin: sOE 1, 2, 3 All -1 +1 A Pins: REF, FB_IN 1, 2, 3 All -5 +5 3-level input DC current I
44、3L3/ HIGH, VIN= VDD_C1, 2, 3 All +200 A MID, VIN= VDD_C/2 -50 +50 LOW, VIN= VSS_C-200 Input pin capacitance, (2-level inputs) CIN-2L4/ f = 1 MHz 0 V See 4.4.1.c REF, FB_IN 4 All 6 typical pF sOE 4 All 9 typical Input pin capacitance, (3-level inputs) CIN-3L4/ f = 1 MHz 0 V See 4.4.1.c 4 All 12 typic
45、al pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical per
46、formance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C +3.0 V (VDD_A/C) +3.6 V unless otherwise specified Group A subgroups Device type Limits 2/ Unit Min Max DC Electrical Characteristics LVDS inputs. 5/ Differential input high threshold voltage VTH 6/ VCM= +1.2 V 1, 2, 3 All
47、 (VCM + 0.1) V Differential input low threshold voltage VTL 6/ VCM= +1.2 V 1, 2, 3 All (VCM- 0.1) V Common mode voltage range VCMR 7/ VID= 200 mV peak-to-peak 1, 2, 3 All 0.1 2.3 V Negative input clamp voltage VIC-For input under test: IIN= -18 mA 1, 2, 3 All -1.5 -0.4 V Input leakage current ILVDIN
48、For input under test: VIN= +3.6 V or 0.0 V; VDD_C= +3.6 V 1, 2, 3 All -15.0 +15.0 A Input cold spare leakage current ICSFor input under test: VIN= +3.6 V VDD_C= 0.0 V 1, 2, 3 All -5.0 +5.0 A Input pin capacitance CLVDIN4/ f = 1 MHz 0 V See 4.4.1.c 4 All 7 typical pF DC Electrical Characteristics XTAL_IN inputs High-level input voltage VIH1, 2, 3 All (0.55* VDD_C) V Low-level input voltage VIL1, 2, 3 All (0.35* VDD_C) V Positive input clamp voltage VIC+For input under test: IIN= +18 mA; VDD_C= 0.0 V 1, 2, 3 All +0.4 +1.5 V Negative
