1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Figure 1, case outline X, corrected the “e” dimension. Updated drawing to remove class M requirements. - drw 12-07-25 Charles F. Saffle REV SHEET REV A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV A A A A A A A A A A A A A
2、 A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Raj Pith
3、adia APPROVED BY Charles F. Saffle MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, 1 GSPS, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 11-07-01 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-09240 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E416-12 Provided by IHSNot for ResaleNo
4、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting o
5、f high reliability (device classes Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. T
6、he PIN is as shown in the following example: 5962 - 09240 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RH
7、A marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 ADS5400-SP 12 bit, 1 G
8、SPS, analog to digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outli
9、ne is as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 100 Ceramic nonconductive tie-bar package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535. Provided by IHSN
10、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/, 2/ Supply voltage: 5 V analog supply volt
11、age (AVDD5) to ground (GND) 6 V 3 V analog supply voltage (AVDD3) to GND 5 V 3 V digital supply voltage (DVDD3) to GND . 5 V AINP, AINN to GND (voltage difference between pin and ground) 0.5 V to 4.5 V 3/ AINP to AINN (voltage difference between pins, common mode at AVDD5/2 ): 3/ Short duration . -0
12、.3 V to (AVDD5 + 0.3 V) Continuous AC signal . 1.25 V to 3.75 V Continuous DC signal . 1.75 V to 3.25 V CLKINP, CLKINN to GND (voltage difference between pin and ground) . 0.5 V to 4.5 V 3/ CLKINP to CLKINN (voltage difference between pins, common mode at AVDD5/2 ): 3/ Continuous AC signal . 1.1 V t
13、o 3.9 V Continuous DC signal . 2 V to 3 V RESETP, RESETN to GND (voltage difference between pin to ground) . -0.3 V to (AVDD5 + 0.3 V) 3/ RESETP to RESETN (voltage difference between pins): 3/ Continuous AC signal . 1.1 V to 3.9 V Continuous DC signal . 2 V to 3 V Data/OVR outputs to GND (voltage di
14、fference between pin and ground) -0.3 V to (DVDD3 + 0.3 V) 3/ SDENB, SDIO, SCLK to GND (voltage difference between pin and ground) . -0.3 V to (AVDD3 + 0.3 V) 3/ ENA1BUS, ENPWD, ENEXTREF to GND (voltage difference between pin and ground) -0.3 V to (AVDD5 + 0.3 V) 3/ Maximum junction temperature (TJ)
15、 . 150C Storage temperature range -65C to +150C Electrostatic discharge (ESD) rating: Human body model (HDM) . 2 kV Thermal resistance, junction-to-case (JC) 0.849C/W Thermal resistance, junction-to-ambient (JA) . 21.81C/W 1.4 Recommended operating conditions. Supply voltage: AVDD5 to GND . 4.75 V t
16、o 5.25 V AVDD3 to GND . 3.135 V to 3.465 V DVDD3 to GND 3.135 V to 3.465 V Analog input: Full scale differential input range 1.52 VPPto 2 VPPDigital output: Differential output load 5 pF Clock (CLK) input: CLK input sample rate (sine wave) . 100 MSPS to 1000 MSPS Clock amplitude, differential 0.6 VP
17、Pto 1.5 VPPClock duty cycle 45% to 55% Case operating temperature range (TC) -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ This package has built in v
18、ias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low impedance ground path, a thermal land is required on the surface of the printed circuit board (PCB) directly underneath the body of the package. Durin
19、g normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite
20、side of the PCB) that provide for more efficient heat removal. The manufacturer recommends an 11.9 mm2board mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias mus
21、t be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential. 3/ Valid when supplies are within recommended operating range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO
22、CIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the ex
23、tent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Meth
24、od Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.
25、mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in
26、 this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in th
27、e device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein
28、 for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing wave
29、forms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall app
30、ly over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted wit
31、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit
32、unless otherwise specified Min Max Analog inputs section Full scale differential input range Programmable 1, 2, 3 01 1.52 2 VPPReference voltage VREF1, 2, 3 01 1.98 2.02 V Dynamic accuracy section Resolution No missing codes 4, 5, 6 01 12 Bits Differential linearity error DNL fIN= 125 MHz 4, 5, 6 01
33、 -1 2.5 LSB Integral non- linearity error INL fIN= 125 MHz 4, 5, 6 01 -4.5 4.5 LSB Offset error voltage Default is trimmed near 0 mV 1, 2, 3 01 -2.5 2.5 mV Power supply section 2/ 5 V analog supply current (Bus A and B active) IAVDD5fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 245 mA 5 V analog supply curren
34、t (Bus A active) IAVDD5fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 255 mA 3.3 V analog supply current (Bus A and B active) IAVDD3fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 234 mA 3.3 V analog supply current (Bus A active) IAVDD3fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 242 mA 3.3 V digital supply current (Bus A and B ac
35、tive) IDVDD3fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 154 mA 3.3 V digital supply current (Bus A active) IDVDD3fIN= 125 MHz, fS= 1 GSPS 1, 2, 3 01 85 mA Total power dissipation (Bus A and B active) 1, 2, 3 01 2.5 W Total power dissipation (Bus A active) 1, 2, 3 01 2.3 W Total power dissipation ENPWD = log
36、ic high (sleep enabled) 1, 2, 3 01 50 mW See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM
37、 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Dynamics ac characteristics section Signal to noise ratio SNR fIN= 125 MHz 4, 5, 6 01 54 dBFS fIN= 600 MHz 53.5
38、 fIN= 850 MHz 53 Spurious free dynamic range SFDR fIN= 125 MHz 4, 5, 6 01 62 dBc fIN= 600 MHz 60 fIN= 850 MHz 56 Second harmonic HD2 fIN= 125 MHz 4, 5, 6 01 62 dBc fIN= 600 MHz 60 fIN= 850 MHz 56 Third harmonic HD3 fIN= 125 MHz 4, 5, 6 01 62 dBc fIN= 600 MHz 60 fIN= 850 MHz 56 Worst harmonic/spur (o
39、ther than fIN= 125 MHz 4, 5, 6 01 62 dBc HD2 and HD3) fIN= 600 MHz 60 fIN= 850 MHz 56 Total harmonic distortion THD fIN= 125 MHz 4, 5, 6 01 60 dBc fIN= 600 MHz 58 fIN= 850 MHz 55 Signal to noise and distortion SINAD fIN= 125 MHz 4, 5, 6 01 53 dBFS fIN= 600 MHz 52.4 fIN= 850 MHz 50.8 Effective number
40、 of bits ENOB fIN= 125 MHz 4, 5, 6 01 8.52 Bits (using SINAD in dBFS) fIN= 600 MHz 8.42 fIN= 850 MHz 8.16 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARI
41、TIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 3/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Switching characteristics LVDS digital outputs
42、 (DATA, OVR/SYNCOUT, CLKOUT) Differential output voltage() VODTerminated 100 differential 1, 2, 3 01 247 454 mV Common mode output voltage VOCTerminated 100 differential 1, 2, 3 01 1.125 1.375 V LVDS digital inputs (RESET) Differential input voltage() VIDEach input pin 1, 2, 3 01 175 mV Common mode
43、input voltage VICEach input pin 1, 2, 3 01 0.1 2.4 V Digital inputs (SCLK, SDIO, SDENB) High level input voltage VIH1, 2, 3 01 2 AVDD3 + 0.3 V Low level input voltage VIL1, 2, 3 01 0 0.8 V V Digital inputs (ENEXTREF, ENPWD, ENA1BUS) High level input voltage VIH1, 2, 3 01 2 AVDD5 + 0.3 V Low level in
44、put voltage VIL1, 2, 3 01 0 0.8 V V Digital outputs (SDIO, SDO) High level output voltage VOHIOH= 250 A 1, 2, 3 01 2.8 V Low level output voltage VOLIOL= 250 A 1, 2, 3 01 0.4 V Clock inputs Differential input resistance RINCLKINP, CLKINN 4, 5, 6 01 100 190 See footnotes at end of table. Provided by
45、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-09240 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol
46、Conditions 3/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max LVDS output timing (DATA, CLKOUT, OVR/SYNCOUT) 4/ Clock period tCLK9, 10, 11 01 1 10 ns Clock pulse duration, high tCLKHAssuming worst case 45/55 duty cycle 9, 10, 11 01 0.45 ns Clock pulse durat
47、ion, low tCLKLAssuming worst case 45/55 duty cycle 9, 10, 11 01 0.45 ns Setup time, single bus mode 5/, 6/ tSU-SBMData valid to CLKOUT edge, 50% CKLIN duty cycle 9, 10, 11 01 290 ps Hold time, single bus mode 6/ tH-SBMCLKOUT edge to data invalid, 50% CLKIN duty cycle 9, 10, 11 01 410 ps Setup time,
48、dual bus mode 6/ tSU-DBMData valid to CLKOUT edge, 50% CKLIN duty cycle 9, 10, 11 01 550 ps Hold time, dual bus mode 6/ tH-DBMCLKOUT edge to data invalid, 50% CLKIN duty cycle 9, 10, 11 01 1150 ps LVDS input timing (RESETIN) RESET setup time 6/ tRSURESETP going high to CLKINP going low 9, 10, 11 01 325 ps RESET hold time 6/ tRHCLKINP going low to RESETP going low 9, 10, 11 01 325 ps Serial interface timing Setup time, serial enable tS-SDE
