1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.
2、mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Laura Leeper THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2MEG X 32-BIT (64M), RADIATION-HARDENED, DUAL VOLTAGE SRAM with embedded EDAC, M
3、ULTICHIP MODULE DRAWING APPROVAL DATE 12-09-24 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-10203 SHEET 1 OF 31 DSCC FORM 2233 APR 97 5962-E212-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10203
4、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finish
5、es are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 10203 01 Q X A Federal RHA Device Device Case Lead stock cla
6、ss designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desig
7、nator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 UT8ER2M32M 2M X 32-bit rad-hard SRAM master 22 ns 02 UT8ER2M32S 2M X 32-bit rad-hard SRAM slave 22 ns 03 UT8ER
8、2M32M 2M X 32-bit rad-hard SRAM master, with additional screening 1/ 22 ns 04 UT8ER2M32S 2M X 32-bit rad-hard SRAM slave, with additional screening 1/ 22 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device
9、class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 132 dual cavity quad flat pack
10、1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. 1/ Device types 03 and 04 provides QML Q product with additional testing as specified in paragraph 4.2.1d. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
11、STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (VDD1) . -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) . -0.3 V dc to +3.8 V dc Voltage range o
12、n any pin . -0.3 V dc to +3.8 V dc Input current, dc . + 10 mA Power dissipation permitted, PD TC= 105C 2.0 W 4/ Case temperature range, (TC) . -55C to +105C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, junction-to-case, (JC): Case X 10C/W 1.
13、4 Recommended operating conditions. 3/ Supply voltage range, (VDD1) . +1.7 V dc to +2.0 V dc Supply voltage range, (VDD2) . +2.3 V dc to +3.6 V dc Supply voltage, (VSS) . 0 V dc Input voltage, dc 0 V dc to VDD2Case operating temperature range, (TC) -55C to +105C 1.5 Radiation features Maximum total
14、dose available (effective dose rate = 1 rads(Si)/s). 10.0 x 104rads(Si) 5/ Single event phenomenon (SEP) effective linear energy threshold (LET) with no upsets N/A 6/ with no latch-up . 100 errors or 106ions/cm2. c. The flux shall be between 102and 105ions/cm2/s. The cross-section shall be verified
15、to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The test temperature shall be +25C 10C for single event upset testing and at the maximum rated operating temperature +10C f
16、or single event upset testing. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10203
17、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 29 DSCC FORM 2234 APR 97 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this draw
18、ing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.2 Configu
19、ration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land a
20、nd Maritime when a system application requires configuration control and which SMDs are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
21、 devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614)692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols
22、, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (s
23、ee 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of trans
24、ients (SEP). e. Occurrence of latchup (SEP). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 30 DSCC FORM 2234 APR 97 APPENDIX A Appe
25、ndix A forms a part of SMD 5962- 10203 FUNCTIONAL ALGORITHMS A.1 SCOPE A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the devic
26、e. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose. Each man
27、ufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information contained herein is intended for compliance. A.2 APPLICABLE DOCUMENTS. This section is not
28、applicable to this appendix. A.3 ALGORITHMS A.3.1 Algorithm A (pattern 1). A.3.1.1 Checkerboard, checkerboard-bar. Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum. Step 2. Read memory, verifying the output checkerboard pattern by incrementing from loca
29、tion 0 to maximum. Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum. Step 4. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum. A.3.2 Algorithm B (pattern 2). A.3.2.1 March. Step 1. Load memory with bac
30、kground data, incrementing from minimum to maximum address locations (all “0s“). Step 2. Read data in location 0. Step 3. Write complement data to location 0. Step 4. Read complement data in location 0. Step 5. Repeat steps 2 through 4 incrementing X-fast sequentially for each location in the array.
31、 Step 6. Read complement data in maximum address location. Step 7. Write data to maximum address location. Step 8. Read data in maximum address location. Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array. Step 10. Read data in location 0. Step 11. Write
32、 complement data to location 0. Step 12. Read complement data in location 0. Step 13. Repeat steps 10 through 12 decrementing X-fast sequentially for each location in the array. Step 14. Read complement data in maximum address location. Step 15. Write data to maximum address location. Step 16. Read
33、data in maximum address location. Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array. Step 18. Read background data from memory, decrementing X-fast from maximum to minimum address locations. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
