1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated to current MIL-PRF-38535 requirements. Corrected the 2.3 V VDDD 2.7 V maximum limit for tBLQV and tGLQV in table IA. Corrected test conditions for IDDDOPR1 and IDDDOPR40. Corrected subscripts in symbols IILK and IOLK in table IIB. Correct
2、ed 6.7 for CE, VDD and VDDD. lhl 13-12-11 Charles F. Saffle REV SHEET REV A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Laura Turner DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 h
3、ttp:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Laura Turner APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2M X 32-BIT (64Mb), RADIATION-HARDENED, SRAM, MULTI
4、-CHIP MODULE DRAWING APPROVAL DATE 13-03-22 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-10232 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E087-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10232 D
5、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finis
6、hes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H 10232 01 Q X C Federal stock class designator RHA designato
7、r (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator
8、. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function 01 HXSR06432 2M X 32-bit rad-hard CMOS SRAM 1.2.3 Device class designator. The device class designator shall be a single letter id
9、entifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Pac
10、kage style X See figure 1 86 Flat pack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10232 DLA LAND AND MARITIM
11、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range I/O (VDDD) . -0.5 V dc to +4.4 V dc Supply voltage range Core (VDD) . -0.5 V dc to +2.4 V dc DC input voltage range (VIN) -0.5 V dc to VDDD + 0.5 V dc DC output voltage
12、 range (VOUT) . -0.5 V dc to VDDD + 0.5 V dc DC or average output current (IOUT) 15 mA Storage temperature -65C to +150C Lead temperature (soldering 5 seconds) +270C Thermal resistance, junction to case (JC) . 5.0 C/W Voltage applied to pins, except power . -0.5 V dc to VDDD + 0.5V dc Maximum power
13、dissipation . 2.5 W Case operating temperature range (TC) . -55C to +125C Maximum junction temperature (TJ) . 175C 1.4 Recommended operating conditions. 3/ Supply voltage range I/O (VDDD) . 3.0 V dc to 3.6 V dc Optional Supply voltage range I/O (VDDD) . 2.3 V dc to 2.7 V dc Supply voltage range Core
14、 (VDD) . 1.65 V dc to 1.95 V dc Supply voltage reference (VSS) 0.0 V dc High level input voltage range (VIH) 0.75 x VDDD to VDDD + 0.3 V dc Low level input voltage range (VIL) . -0.3 V dc to 0.25 x VDDD Voltage on any pin (VIN) . -0.3 V dc to VDDD + 0.3 Power Down Time 5 ms minimum 4/ Case operating
15、 temperature range (TC) -55C to +125C VDD/VDDD Voltage Ramp Time . 1.0 second maximum 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . 100 percent 1.6 Radiation features. 5/ Maximum total dose available (d
16、ose rate = 50-300 rad(Si)/s) 1 x 106 Rads(Si) Single event phenomenon (SEP): Heavy Ion Single event upset (SEU) rate 1 x 10-12 upsets/bit-day 6/ Proton Single event upset (SEU) rate 2 x 10-12 upsets/bit-day 6/ Neutron irradiation . 1 x 10-14 neutrons/cm2 7/ Dose rate induced upset 1 x 1010 Rad(Si)/s
17、ec for 100 errors or 107 ions/cm2. c. The flux shall be between 102 and 106 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e.
18、 The test temperature shall be +25C for upset and the maximum rated operating temperature +125C for latchup. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. For SEP test limits, see table IB herein. 4.4.4.5 Neutron testing. When required by the customer, neutron
19、testing shall be performed in accordance with method 1017 of MIL-STD-883 and herein. All device classes must meet the post irradiation end-point electrical parameter limits as defined in table IA, for the subgroups specified in Table IIA herein at TA = +25 C 5 C after an exposure of 2 x 1012 neutron
20、s/cm2 (minimum). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10232 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 20 DSCC FORM 2234 APR 97 4.5 Delta measurements for device class V
21、. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer
22、 may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q, and V. 6. N
23、OTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by
24、 a contractor prepared specification or drawing. 6.2 Configuration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of u
25、sers. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMDs are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes
26、 to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990 or telephone (614) 692-0540. 6.5 Abbrevi
27、ations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535.
28、The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10232 D
29、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 21 DSCC FORM 2234 APR 97 6.7 Signal definitions. A (0-18) Address input signals. Used to select a particular 32 bit word within the memory array. DQ (0-31) Bi-directional data signals. These function as data outputs during a read
30、operation and as data inputs during a write operation. NCS Negative Chip Select input signal. Setting to a low level allows normal read or write operation. When at a high level, it sets the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state. If the NCS signal
31、is not used it must be connected to VSS. NWE Negative Write Enable input signal. Setting to a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. NOE Negative Output Enable input signal. Setting to a
32、 high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NBE, CE and NWE. If this signal is not used, it must be connected to VSS. CE Chip Enable input signal. When set to a high level, the SRAM is in normal read or wri
33、te operation. When at a low level, it defaults the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state. If the CE signal is not used, it must be connected to VDDD. NBE (0-3) Not Byte Enable input signal. When set to a low level, enables a read or write operatio
34、n on a specific byte within the 32 bit (4 byte) word. When at a high level, the write operation of a specific byte is disabled and during a read operation the 8 data outputs of the specific byte are held in a high impedance state. VDD SRAM Core operating voltage (typical 1.8V) VDDD I/O Operating vol
35、tage (typical 3.3V) Cathode and Anode These signals are used for manufacturing test only. They shall be connected to VSS. 6.8 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA test conditions (SEP).
36、 b Number of upsets (SEU). c. Number of transients (SET). d. Occurrence of latchup (SEL). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10232 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A
37、 SHEET 22 DSCC FORM 2234 APR 97 APPENDIX A Appendix A forms a part of SMD 5962-10232 FUNCTIONAL ALGORITHMS A.1 SCOPE A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper operation of a random access memory (RAM). Each algorithm serves a
38、 specific purpose for the testing of the device. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns
39、 be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information contained herein is intended for compliance.
40、A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix. A.3 ALGORITHMS A.3.1 Algorithm A (pattern 1). A.3.1.1 Checkerboard, checkerboard-bar. Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum. Step 2. Read memory, verifying the output
41、checkerboard pattern by incrementing from location 0 to maximum. Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum. Step 4. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum. A.3.2 Algorithm B (pattern 2
42、). A.3.2.1 March left - right. Step 1. Increment address from minimum to maximum writing each address with alternating data pattern (x55). Step 2. Increment address from minimum to maximum while performing 2a and 2b Step 2a. Read and verify an address. Step 2b. Write the address with complement data
43、. Step 3. Decrement address from maximum to minimum while performing 3a, 3b, 3c, 3d Step 3a. Read and verify an address. Step 3b. Write the address with complement data. Step 3c. Read and verify the address. Step 3d. Write the address with complement data. Step 4. Decrement address from maximum to m
44、inimum while performing 4a and 4b Step 4a. Read and verify the address Step 4b. Write the address with complement data Step 5. Decrement address from maximum to minimum while performing 5a, 5b, 5c, and 5d Step 5a. Read and verify the address Step 5b. Write the address with complement data Step 5c. R
45、ead and verify the address Step 5d. Write the address with complement data Step 6. Decrement address from maximum to minimum while performing 6a Step 6a. Read and verify the address Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI
46、T DRAWING SIZE A 5962-10232 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 23 DSCC FORM 2234 APR 97 APPENDIX A - Continued. Appendix A forms a part of SMD 5962-10232 FUNCTIONAL ALGORITHMS A.3.3 Algorithm C (pattern 3). A.3.3.1 Solids. Step1. Write x00 data pattern to all addr
47、esses from minimum to maximum. Step 2. Read and verify x00 data pattern at all addresses. Step 3. Write xFF data pattern to all addresses from minimum to maximum. Step 4. Read and verify xFF data pattern at all addresses. A.3.4 Algorithm D (pattern 4). A.3.4.1 Control signals functional Verification
48、. Each test performed independently. NOE Functional test: Read with NOE = VIH and confirm high-Z outputs NCS Functional test: Read with NCS = VIH and verify high-Z outputs Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-12-11 Approved sources of supply for SMD 5962-10232 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next r
