1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWIN
2、G THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Charles F. Saffle MICROCIRCUIT, LINEAR, RADIATION HARDENED, CMOS, 16 TO 1 ANALOG MULTIPLEXER, MONOLITHIC SILICON DRAWING APPROVAL DATE 12-07-17 AMSC N/A REVISION LE
3、VEL SIZE A CAGE CODE 67268 5962-10236 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E428-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEE
4、T 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Num
5、ber (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F 10236 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outlin
6、e (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device t
7、ypes identify the circuit function as follows: Device type Generic number Circuit function 01 UT16MX115 Radiation hardened, CMOS 16 channel MUX, serial address interface 02 UT16MX113 Radiation hardened, CMOS 16 channel MUX, asynchronous parallel address interface 03 UT16MX114 Radiation hardened, CMO
8、S 16 channel MUX, synchronous parallel address interface 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case
9、 outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 28 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reprod
10、uction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage between AVDDand AVSS. 7.8 V Digital supply voltage
11、between VDDand GND . 4.5 V Power dissipation 150 mW Junction temperature (TJ) range . -55C to +130C Storage temperature (TSTG) range -65C to +150C ESDHBM 2kV 2/ Thermal resistance, junction -to-case (JC) 4.8C/W 1.4 Recommended operating conditions. Analog positive supply voltage (AVDD) 4.5 V to 5.5
12、V Analog negative supply voltage (AVSS) . 0 V Digital supply voltage referenced to GND (VDD) 3.0 V to 3.6 V Analog Input voltage (VIN) . AVSSto AVDDDigital Input voltage (VI) 0 V to VDDCase operating temperature range (TC) -55C to +125C Junction temperature operating range (TJ) . -55C to +130C 1.5 R
13、adiation features. Maximum total dose available (dose rate = 50 300 rads(Si)/s) 3 x 105rads(Si) 3/ Single event phenomenon (SEP): Effective linear energy transfer (LET), no upsets . 62.3 MeV-cm2/mg 4/ Effective linear energy transfer (LET), no latch-up 110 MeV-cm2/mg 4/ 2. APPLICABLE DOCUMENTS 2.1 G
14、overnment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIF
15、ICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standa
16、rd Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absol
17、ute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Test per MIL-STD-883, Method 3015.7. 3/ Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in
18、MIL-STD-883, method 1019, condition A. 4/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR
19、CUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are
20、 the issues of the documents cited in the solicitation or contract. ASTM INTERNATIOINAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices (Copies of this document are available online at http:/ www.astm.or
21、g/ or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however,
22、supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Qu
23、ality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and
24、 V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Block diagram. The block diagram shall
25、 be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics an
26、d postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test re
27、quirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN n
28、umber is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/com
29、pliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements o
30、f this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Ce
31、rtificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC
32、IRCUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, VDD= 3.3 V0.3 V, AVSS= 0 V, GND = 0 V Group A subgroups Device
33、 type Limits Unit unless otherwise specified Min Max DC Electrical Characteristics Digital input low VILVDD= 3.0 V 1, 2, 3 All -0.3 0.8 V Digital input high VIHVDD= 3.0 V 1, 2, 3 All 2.0 V Digital output low VOLVDD= 3.0 V, IOL= 100 A 1, 2, 3 01 0.2 V VDD= 3.0 V, IOL= 2 mA 0.4 Digital output high VOH
34、VDD= 3.0 V, IOH= -100 A 1, 2, 3 01 2.8 V VDD= 3.0 V, IOH= -2 mA 2.4 On resistance RONVIN= AVSSto AVDD, VCOM= VIN 0.3 V 1, 2, 3 All 40 300 Analog I/O leakage current (switch off) 3/ IOFFAVDD= 5.5 V, VDD= 3.6 V, VIN= AVSSor AVDD1, 2, 3 All -1.6 1.6 A Digital input current low IILVDD= 3.6 V, VIL= GND L
35、VCMOS/LVTTL inputs 1, 2, 3 All -1.0 1.0 A Inputs with pull-up -380 -20 Inputs with pull-down 03 -5.0 5.0 Digital input current high IIHVDD= 3.6 V, VIH= VDDLVCMOS/LVTTL inputs 1, 2, 3 All -1.0 1.0 A Inputs with pull-up 4/ -60 60 Inputs with pull-down 03 20 380 Quiescent analog supply current QIDDAVDD
36、= 5.5 V, VDD= 3.6 V, VIH= VDD, VIL= GND 1, 2, 3 All 10 A Quiescent digital supply current QIDD_ VDDAVDD= 5.5 V, VDD= 3.6 V, VIH= VDD, VIL= GND 1, 2, 3 All 250 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M
37、ICROCIRCUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, VDD= 3.3 V0.3 V, AVSS= 0 V, GND = 0 V Group A
38、 subgroups Device type Limits Unit unless otherwise specified Min Max AC Electrical Characteristics Input capacitance (switch off) 5/, 6/ CINFIN= 1 MHz 0 V, See 4.4.1d4 All 50 pF Input capacitance, digital 5/, 6/ CIN_ DIGITALFIN= 1 MHz 0 V, See 4.4.1d4 All 55 pF Output capacitance at COM 5/, 6/ COUT
39、FIN= 1 MHz 0 V, See 4.4.1d4 All 80 pF Off isolation, feed through attenuation (switch off) 5/, 7/ OISORL= 600, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1d 4 All -80 dB Bandwidth (frequency response) 5/, 7/ BW RSOURCE= 50, RL= 2.2 M, CL= 12 pF, VIN= 1 Vp-p, See 4.4.1d 4 All 51 MHz Cross talk (between
40、 any 2 channels) 5/, 7/ XTALK2RL= 1 k, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1d 4 All -80 dB Settling time of output at COM within 1% of final output voltage 5/, 7/ tSRL= 100 k, CL= 50 pF 4 All 120 ns Total harmonic distortion 5/, 7/ THD RL= 1 k, CL= 50 pF, VIN= 5 Vp-p, FIN= 1 MHz sine wave, See
41、4.4.1d 4 All 5.0 % Timing Characteristics Propagation delay of analog signal input (Sx) to analog output (COM) measured at 50% 5/ tPROP_SRT= 50, CL= 50 pF, See figures 10 and 12 9, 10, 11 All 25 ns Propagation delay of any changes in the digital inputs (A3:0, CS/, PLATCH, SS/) affecting the analog o
42、utput (COM). 5/ tPROP_DRT= 50, CL= 50 pF See figures 7 and 12 9, 10, 11 01 25 140 ns See figures 5 and 12 02 See figures 6 and 12 03 Mux decoding time 5/ tMUXRT= 50, CL= 50 pF See figures 7 and 12 9, 10, 11 01 50 ns See figures 5 and 12 02 See figures 6 and 12 03 Break-Before-Make-Delay 5/ tBBMRT= 5
43、0, CL= 50 pF See figures 7 and 12 9, 10, 11 01 15 90 ns See figures 5 and 12 02 See figures 6 and 12 03 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10236 DLA LAND AND MARITI
44、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, VDD= 3.3 V0.3 V, AVSS= 0 V, GND = 0 V Group A subgroups Device type Limits Unit unless otherwise speci
45、fied Min Max Timing Characteristics - continued Output enable time from HiZ to low or high once RESET/ is pulled high 5/ tPZLHRT= 50, CL= 50 pF, See figures 9 and 12 9, 10, 11 01, 03 90 ns Output disable time from low or high to HiZ once RESET/ is pulled low 5/ tPLHZRT= 50, CL= 50 pF, See figures 9
46、and 12 9, 10, 11 01, 03 55 ns SCLK frequency 5/ fSCLKSee figure 7 9, 10, 11 01 2.0 MHz SCLK high time 5/ tHSee figure 7 9, 10, 11 01 190 ns SCLK low time 5/ tLSee figure 7 9, 10, 11 01 190 ns First SCLK setup time (for shifting window) 5/ tSSUSee figure 7 9, 10, 11 01 7.0 ns Last SCLK hold time (for
47、 shifting window) 5/ tSSHSee figure 7 9, 10, 11 01 10 ns Data in (MOSI) setup time wrt rising edge SCLK 5/ tSUSee figure 7 9, 10, 11 01 3.0 ns Data in (MOSI) hold time wrt rising edge SCLK 5/ tHDSee figure 7 9, 10, 11 01 5.0 ns Data out (MISO) valid (after falling edge of SCLK) 5/ tDOCL= 50 pF, See
48、figure 7 9, 10, 11 01 43 ns Data out (MISO) rise time 5/ tDR10-90% VDD, CL= 50 pF 9, 10, 11 01 30 ns Data out (MISO) fall time 5/ tDF10-90% VDD, CL= 50 pF 9, 10, 11 01 20 ns The minimum amount of time required for the address signals (A3:0) to be stable before the falling edge of CS/ 5/, 7/ tAS1See figure
