1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add characterization for device types 01 and 02. Added test conditions to table IIB. Delete class M requirements. - drw 12-08-21 Charles F. Saffle REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS REV A A A A A A A A A A A A A A O
2、F SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY R
3、ajesh Pithadia APPROVED BY Charles F. Saffle MICROCIRCUIT, LINEAR, RADIATION HARDENED, CMOS, 16 TO 1 ANALOG MULTIPLEXER, MONOLITHIC SILICON DRAWING APPROVAL DATE 11-06-23 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-10237 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E451-12 Provided by IHSNot f
4、or ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels c
5、onsisting of high reliability (device classes Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
6、 1.2 PIN. The PIN is as shown in the following example: 5962 F 10237 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes
7、 Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 UT16MX117 R
8、adiation hardened, CMOS 16 channel MUX, serial address interface 02 1/ UT16MX117 Radiation hardened, CMOS 16 channel MUX, serial address interface with additional screening 03 UT16MX116 Radiation hardened, CMOS 16 channel MUX, asynchronous parallel address interface 04 1/ UT16MX116 Radiation hardene
9、d, CMOS 16 channel MUX, asynchronous parallel address interface with additional screening 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualific
10、ation to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 28 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. _ 1/
11、Device types 02 and 04 provide a QML-Q product with the additional testing as specified in section 4.2.1.d herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 43
12、218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage between AVDDand AVSS. 7.8 V Digital I/O supply voltage between VDD_IOand GND . 6.5 V Digital supply voltage between VDDand GND . 4.5 V Power dissipation 150 mW Junction temperature (TJ) range . -5
13、5C to +130C Storage temperature (TSTG) range -65C to +150C ESDHBM 2 kV 2/ Thermal resistance, junction -to-case (JC) 4.8C/W 1.4 Recommended operating conditions. Analog positive supply voltage (AVDD) 4.5 V to 5.5 V Analog negative supply voltage (AVSS) . 0 V Digital I/O supply voltage referenced to
14、GND (VDD_IO) 3.0 V to 5.5 V Digital supply voltage referenced to GND (VDD) 3.0 V to 3.6 V Analog input voltage (VIN) . AVSSto AVDDDigital input voltage (VI) 0 V to VDD_IOCase operating temperature range (TC) -55C to +125C Junction temperature operating range (TJ) . -55C to +130C 1.5 Radiation featur
15、es. Maximum total dose available (dose rate = 50 300 rads(Si)/s) 3 x 105rads(Si) 3/ Single event phenomenon (SEP): Effective linear energy transfer (LET), no upsets . 62.3 MeV-cm2/mg 4/ Effective linear energy transfer (LET), no latch-up 110 MeV-cm2/mg 4/ 2. APPLICABLE DOCUMENTS 2.1 Government speci
16、fication, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF
17、-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit
18、 Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rat
19、ing may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Test per MIL-STD-883, Method 3015.7. 3/ Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, me
20、thod 1019, condition A. 4/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI
21、ZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues o
22、f the documents cited in the solicitation or contract. ASTM INTERNATIOINAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices (Copies of this document are available online at http:/ www.astm.org/ or from AS
23、TM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes ap
24、plicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Managem
25、ent (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Cas
26、e outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Block diagram. The block diagram shall be as specif
27、ied on figure 11. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradi
28、ation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements s
29、hall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not
30、 feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark
31、. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawi
32、ng (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of
33、 conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWI
34、NG SIZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, VDD= 3.3 V0.3 V, VDD_IO= 3.0 V to 5.5 V, GND = 0 V Group A subgroups Dev
35、ice type Limits Unit unless otherwise specified Min Max DC Electrical Characteristics Digital input low VILVDD_IO= 3.0 V 1, 2, 3 All -0.3 0.8 V VDD_IO= 4.5 V 1.35 Digital input high VIHVDD_IO= 3.0 V 1, 2, 3 All 2.0 V VDD_IO= 4.5 V 3.15 Digital output low VOLVDD_IO= 3.0 V, IOL= 100 A 1, 2, 3 01, 02 0
36、.2 V VDD_IO= 3.0 V, IOL= 2 mA 0.4 VDD_IO= 4.5 V, IOL= 2 mA 0.5 Digital output high VOHVDD_IO= 3.0 V, IOH= -100 A 1, 2, 3 01, 02 2.8 V VDD_IO= 3.0 V, IOH= -2 mA 2.4 VDD_IO= 4.5 V, IOH= -2 mA 3.7 On resistance RONVIN= AVSSto AVDD, VCOM= VIN- 0.3 V 1, 2, 3 All 40 300 Functional tests See 4.4.1b 7, 8A,
37、8B All Analog I/O leakage current (switch off) 3/ IOFFAVDD= 5.5 V, VDD= 3.6 V, VDD_IO= 5.5 V, VIN= AVSSor AVDD1, 2, 3 All -1.6 1.6 A Digital input current low IILVDD_IO= 5.5 V, VIL= GND LVCMOS/CMOS inputs 1, 2, 3 All -1.0 1.0 A Inputs with pull-up -380 -20 Digital input current high IIHVDD_IO= 5.5 V
38、, VIH= VDD_IOLVCMOS/CMOS inputs 1, 2, 3 All -1.0 1.0 A Inputs with pull-up -25 25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 4321
39、8-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, VDD= 3.3 V0.3 V, VDD_IO= 3.0 V to 5.5 V, GND = 0 V Group A subgroups Device type Limits Unit unless otherwise specified Mi
40、n Max DC Electrical Characteristics - continued Quiescent analog supply current QIDDAVDD= 5.5 V, VDD= 3.6 V, VDD_IO= 5.5 V, VIH= VDD_IO, VIL= GND 1, 2, 3 All 10 A Quiescent digital I/O supply current (CMOS) QIDD_IO_CMOSAVDD= 5.5 V, VDD= 3.6 V, VDD_IO= 5.5 V, VIH= VDD_IO, VIL= GND 1, 2, 3 All 2.2 mA
41、Quiescent digital I/O supply current (LVCMOS) QIDD_IO_LVCMOSAVDD= 5.5 V, VDD= 3.6 V, VDD_IO= 3.6 V, VIH= VDD_IO, VIL= GND 1, 2, 3 All 2.0 A Quiescent digital supply current QIDD_ VDDAVDD= 5.5 V, VDD= 3.6 V, VDD_IO= 5.5 V, VIH= VDD_IO, VIL= GND 1, 2, 3 All 40 A AC Electrical Characteristics Input ana
42、log capacitance (switch off) 4/, 5/ CINFIN= 1 MHz 0 V, See 4.4.1c4 All 20 pF Input digital capacitance 4/, 5/ CIN_ DIGITALFIN= 1 MHz 0 V, See 4.4.1c4 All 55 pF Output capacitance at COM 4/, 5/ COUTFIN= 1 MHz 0 V, See 4.4.1c4 All 40 pF Off isolation, feed through attenuation (switch off) 4/, 6/ OISOR
43、L= 600, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1c 4 All -80 dB Bandwidth (frequency response) 4/, 6/ BW RSOURCE= 50, RL= 2.2 M, CL= 12 pF, VIN= 1 Vp-p, See 4.4.1c 4 All 51 MHz Cross talk (between any 2 channels) 4/, 6/ XTALK2RL= 1 k, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1c 4 All -80 dB Settlin
44、g time of output at COM within 1% of final output voltage 4/, 6/ tSRL= 100 k, CL= 50 pF 9 All 120 ns Total Harmonic Distortion 4/, 6/ THD RL= 1 k, CL= 50 pF, See 4.4.1c FIN= 1 MHz sine wave, VIN= 5 Vp-p4 All 5.0 % See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network
45、ing permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10237 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.
46、0 V0.5 V, VDD= 3.3 V0.3 V, VDD_IO= 3.0 V to 5.5 V, GND = 0 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Timing Characteristics Propagation delay of analog signal input (Sx) to analog output (COM) measured at 50%. 4/ tPROP_SRT= 50, CL= 50 pF, See figures 8 and 10 9,
47、10, 11 All 25 ns Propagation delay of any changes in the digital inputs (A3:0, CS/, SS/) affecting the analog output (COM). 4/ tPROP_DRT= 50, CL= 50 pF, See figures 4, 5, and 10 9, 10, 11 All 25 140 ns Mux decoding time 4/ tMUXRT= 50, CL= 50 pF, See figures 4, 5, and 10 9, 10, 11 All 50 ns Break-Bef
48、ore-Make-Delay 4/ tBBMRT= 50, CL= 50 pF, See figures 4, 5, and 10 9, 10, 11 All 15 90 ns Output enable time from HiZ to low or high once RESET/ is pulled low. 4/ tPZLHRT= 50, CL= 50 pF, See figures 7 and 10 9, 10, 11 01, 02 90 ns Output disable time from low or high to HiZ once RESET is pulled high. 4/ tPLHZRT= 50, CL= 50 pF, See f
