DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf

上传人:orderah291 文档编号:698655 上传时间:2019-01-02 格式:PDF 页数:19 大小:218.13KB
下载 相关 举报
DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf_第1页
第1页 / 共19页
DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf_第2页
第2页 / 共19页
DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf_第3页
第3页 / 共19页
DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf_第4页
第4页 / 共19页
DLA SMD-5962-81015 REV D-2012 MICROCIRCUIT MEMORY DIGITAL DYNAMIC 16K RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON.pdf_第5页
第5页 / 共19页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Page 4: Corrections to VIH, IDD1, and tREFlimits. 82-12-14 N. A. Hauck B Change to military drawing format. Change from suggested source to an approved source drawing and add CAGE 66632 87-07-11 N. A. Hauck C Boilerplate update, part of 5 year re

2、view. Deleted burn-in steady-state life test figures and put under document control per revised boilerplate paragraph. REDRAWN ksr 06-04-03 Raymond Monnin D Updated body of drawing to meet current requirements. - glg 12-06-22 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLAC

3、ED REV SHEET REV D D D D SHEET 15 16 17 18 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime

4、.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, MEMORY, DIGITAL, DYNAMIC 16K RANDOM ACCESS MEMORY (RAM), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 82-05-18 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 81

5、015 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E404-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.

6、1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 81015 01 F A Drawing number Device type (see 1

7、.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 5403003 16,384/1-bit random access memory 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1

8、835 and as follows: Outline letter Descriptive designator Terminals Package style F GDFP2-F16or CDFP3-F16 16 flat package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Voltage on any pin relative to substrate -0.3 Vdc to +20 Vdc Storag

9、e temperature range (ambient) -60C to +150C Maximum power dissipation (PD) 1/ 1.0 W Lead temperature (soldering, 5 seconds) . +270C Thermal resistance, junction-to-case (JC): Case F See MIL-STD-1835 Junction temperature (TJ. +150C 1.4 Recommended operating conditions. Supply voltages: VDD10.8 Vdc to

10、 13.2 Vdc VBB-4.5 Vdc to -5.5 Vdc VCC+4.5 Vdc to +5.5 Vdc VSS0.0 Vdc to 0.0 Vdc High level input voltages: Addresses (VIH) . 2.4 Vdc to 7.0 Vdc Clock (VIHC) . 2.7 Vdc to 7.0 Vdc Data in (VIH) 2.4 Vdc to 7.0 Vdc Low level input voltage: All inputs (VIL) . -1.0 Vdc to +0.8 Vdc Case operating temperatu

11、re range (TC) . -55C to +110C Refresh cycle time (tREF) 2.0 ms Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2

12、. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

13、DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS M

14、IL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2

15、.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS

16、 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a

17、 manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan

18、 may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flo

19、w option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth t

20、able shall be as specified on figure 2. 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance

21、 characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Markin

22、g. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in complia

23、nce to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

24、NDARD MICROCIRCUIT DRAWING SIZE A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ Group A subgroups Limits Units Min Max High-level output voltage VOHIOH= -5 mA, VCC= 4.5 V

25、 1, 2, 3 2.4 V Low-level output voltage VOLIOL= 4.2mA, VCC= 4.5 V 1, 2, 3 0.4 V Input leakage current (all inputs) IIL IIHVIN= 0.0 V to 7.0 V 1, 2, 3 -10 +10 A Output leakage current IDL IDHRAS and CAS = VIHC VOUT= 0.0 V to 5.5 V 1, 2, 3 -10 +10 A Supply current from VDDIDD11/ RAS and CAS cycling tR

26、C= 375 ns 1, 2, 3 35 mA IDD2RAS and CAS = VIHC DOUT= High Z 1, 2, 3 1.50 mA IDD31/ RAS cycling tRC = 375 ns CAS = VIHC1, 2, 3 27 mA IDD41/ RAS = VILtRC= 225 ns CAS = cycling 1, 2, 3 27 mA Supply current from VBBIBB11/ RAS and CAS cycling tRC= 375 ns 1, 2, 3 400 A IBB2RAS and CAS = VIHC DOUT= High Z

27、1, 2, 3 200 A IBB31/ RAS cycling tRC= 375 ns CAS = VIHC1, 2, 3 400 A IBB41/ RAS = VILtRC= 225 ns CAS = cycling 1, 2, 3 400 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81015 DLA

28、 LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ Group A subgroups Limits Units Min Max Supply current from VCCICC1RAS and CAS cycling 1, 2, 3 600 A ICC2RAS and CAS = VIHC

29、DOUT= High Z 1, 2, 3 -10 +10 ICC3RAS cycling tRC= 375 ns CAS = VIHC1, 2, 3 -10 +10 ICC4RAS = VILDOUT= High Z CAS = cycling 1, 2, 3 1,000 Functional tests See 4.3.1d 7 Access time from chip select tRCSee figure 4 9, 10, 11 375 ns Read-write cycle time tRWC9, 10, 11 375 ns Page mode cycle time tPCRAS

30、= VIL9, 10, 11 225 ns Access time from RAS tRAC3/ tRCD = minimum 4/ 9, 10, 11 200 ns Access time from CAS tCAC3/ tRCD = minimum 9, 10, 11 135 ns Output buffer turn off delay tOFF9, 10, 11 50 ns RAS precharge time tRP9, 10, 11 120 ns RAS pulse width tRAS9, 10, 11 200 10,000 ns RAS hold time tRSH9, 10

31、, 11 135 ns CAS hold time tCSH9, 10, 11 200 ns CAS pulse width tCAS9, 10, 11 135 10,000 ns RAS to CAS delay time tRCD9, 10, 11 25 65 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

32、A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ Group A subgroups Limits Units Min Max RAS to CAS precharge time tCRP9, 10, 11 0 ns Row address setup time tASR9

33、, 10, 11 0 ns Row address hold time tRAH9, 10, 11 25 ns Column address setup time tASC9, 10, 11 0 ns Column address hold time tCAH9, 10, 11 55 ns Column address hold time referenced to RAS tARSee figure 4 9, 10, 11 125 ns Read command setup time tRCS9, 10, 11 0 ns Read command hold time tRCH9, 10, 1

34、1 0 ns Write command hold time tWCH9, 10, 11 55 ns Write command hold time referenced to RAS tWCR9, 10, 11 120 ns Write command pulse width tWP9, 10, 11 55 ns Write command to RAS lead time tRWL9, 10, 11 80 ns Write command to CAS lead time tCWL9, 10, 11 80 ns Data in setup time to CAS tDSL(c)9, 10,

35、 11 0 ns Data in setup time to write (late write) tDS(w)9, 10, 11 0 ns Data in hold time tDH9, 10, 11 55 ns Data in hold time referenced to RAS tDHR9, 10, 11 120 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

36、RD MICROCIRCUIT DRAWING SIZE A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ Group A subgroups Limits Units Min Max CAS precharge time (page mode only) tCP9, 10

37、, 11 80 ns Refresh period tREF9, 10, 11 2.0 ns Write command setup time tWCS9, 10, 11 0 ns CAS to WRITE delay tCWD9, 10, 11 95 ns RAS to WRITE delay tRWD9, 10, 11 160 ns 1/ Depends on the cycle rate. Limits are for cycle rates listed in conditions column. 2/ Depends on output load. 3/ Load equals on

38、e Schottky TTL + 50 pF or equivalent. 4/ Device type 01 has page mode operation tested. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of complian

39、ce submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-3

40、8535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Mar

41、itimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures

42、 shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-S

43、TD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicab

44、le, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer.

45、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 4.3 Quality conformance inspection. Quality conformance inspecti

46、on shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall

47、be omitted. c. Subgroup 4 (CINand COUT measurement) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 5 d

48、evices with no failures, and all input and output terminals tested. d. Subgroups 7 shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, C, D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power d

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1