1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED E Add minimum limits to propagation delays. Split VILinto temperatures. Change footnotes in table I. Change power dissipation. Editorial changes throughout. -mlp 88-04-05 M. A. Frye F Changes in accordance with NOR 5962-R156-92. 92-07-10 Monica L.
2、Poelking G Redraw with changes. Update to current requirements. Editorial changes throughout. -gap 05-12-08 Raymond Monnin CURRENT CAGE CODE 67268 THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 1
3、0 11 12 13 PMIC N/A PREPARED BY Monica L. Poelking DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, BIPOLAR,
4、ADVANCED LOW-POWER SCHOTTKY TTL, FLIP-FLOPS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 84-01-27 MONOLITHIC SILICON AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 14933 83019 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E515-05 Provided by IHSNot for ResaleNo reproduction or networking p
5、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B mic
6、rocircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 83019 01 E X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identify the circ
7、uit function as follows: Device type Generic number Circuit function 01 54ALS174 Hex D-type flip-flop with clear 02 54ALS175 Quad D-type flip-flop with clear 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Packa
8、ge style E GDIP1-T16 or CDIP2-T16 16 dual-in-line F GDFP2-F16 or CDFP3-F16 16 flat 2 CQCC1-N20 20 square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc minimum to +7.0 V dc maximum
9、Input voltage range -1.5 V dc at -18 mA to +7.0 V dc Storage temperature -65C to +150C Maximum power dissipation (PD) per device 1/: Device type 01 104.5 mW Device type 02 77 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction tempe
10、rature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage (VCC) +4.5 V dc minimum to +5.5 V dc maximum Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL): TC= +125C . 0.7 V dc TC= +25C . 0.8 V dc TC= -55C 0.8 V dc Normalized fanout (each output) 2/ .
11、 10 maximum at low logic level 20 maximum at high logic level Case operating temperature range (TC) -55C to +125C _ 1/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short-circuit test; e.g., IO. 2/ Device will fanout in both high and low levels to the specif
12、ied number of data inputs on the same device as that being tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM
13、2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation
14、or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENS
15、E HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue
16、 Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specifi
17、c exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (
18、QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as
19、documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-
20、38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2
21、 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test ci
22、rcuit and switching waveforms shall be as specified on figure 4 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for
23、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be t
24、he subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Ce
25、rtification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option
26、 is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall
27、 affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.
28、8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore do
29、cumentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall
30、 be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall
31、 be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical tes
32、t parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A
33、 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. 1/ 2/ Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroupsDevice type Limits Unit Min Max High level output vol
34、tage VOHVIL= 0.8 V 1, 3 All 2.5 V VCC= 4.5 V, VIH= 2.0 V, IOH= -0.4 mA 3/ VIL= 0.7 V 2 Low level output voltage VOLVIL= 0.8 V 1, 3 All 0.4 V VCC= 4.5 V, IOL= 4.0 mA, VIH= 2.0 V, 3/ VIL= 0.7 V 2 Input clamp voltage VI CVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.5 V High level input current IIH1VCC= 5.5 V
35、 VIN= 2.7 V, All other inputs = 0.0 V 1, 2, 3 All 20 A IIH2VCC= 5.5 V, VIN= 7.0 V, All other inputs = 0.0 V 100 Low level input current IILCLK inputs 1, 2, 3 All -150 A VCC= 5.5 V, VIN= 0.4 V, All other inputs = 4.5 V Other inputs 1, 2, 3 All -100 A Output current IOVCC= 5.5 V, 4/ VOUT= 2.25 V 1, 2
36、 3 All -20 -112 mA Supply current, ICCVCC= 5.5 V, VIN= 4.5 V, 1, 2, 3 01 19 mA D inputs = 0.0 V, CLR = 0.0 V 02 14 Functional tests See 4.3.1c 5/ 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC
37、IRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics -Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroupsDevice type Limits Unit Min
38、 MaxPropagation delay time, CLK to Q or Q tPLH1VCC= 4.5 V to 5.5 V, CL= 50 pF 10%, 9, 10, 11 All 3 17 ns tPHL1RL= 500 5%, See figure 4 6/ 9, 10, 11 All 5 21.5 Propagation delay time, CLR to Q or Q tPLH29, 10, 11 02 5 19 ns tPHL29, 10, 11 All 8 26 Maximum clock frequency fMAX9, 10, 11 All 40 MHz Puls
39、e duration tw See figure 4 CLR low All 15 ns CLK high All 12.5 CLK low All 12.5 Setup time before CLK tsu Data All 15 ns CLR inactive All 8 Hold time, data after CLK thAll 0 ns 1/ Unused inputs that do not directly control the pin under test must be 2.5 V or 0.4 V. 2/ No unused inputs shall exceed 5
40、5 V or go less than 0.0 V. No inputs shall be floated. 3/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum produces the proper output state, the test must be performed with each input being selected as the VILmaximum or VIHminimum input. 4/ The output conditi
41、ons have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS. Not more than one output will be tested at one time and the duration of the test condition shall not exceed 1 second. 5/ Functional tests shall be conducted at input test condi
42、tions of 0.0 V VIL VOLand VOH VIH VCC. 6/ Propagation delay limits are based on single output switching. Unused inputs = 3.5 V or 0.3 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER
43、COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 FIGURE 1. Terminal connections (top view). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COL
44、UMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 8 DSCC FORM 2234 APR 97 FIGURE 1. Terminal connections (top view). - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS CO
45、LUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 9 DSCC FORM 2234 APR 97 Device type 01 INPUTS OUTPUT CLR CLK D Q L X X L H H H H L L H L X Q0 Device type 02 INPUTS OUTPUT CLR CLK D Q Q L X X L H H H H L H L L H H L X Q0 Q0H = High voltage level L = Low voltage level X = Irrelevant = Transition from l
46、ow to high Q0= Level of Q before the indicated steady-state input conditions were established. Q0= Level of Q before the indicated steady-state input conditions were established. FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,
47、STANDARD MICROCIRCUIT DRAWING SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 10 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWI
48、NG SIZE A 83019 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 11 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses have the following characteristics: PRR 10 MHz, duty cycle = 50 percent, tr= tf= 3 ns 1 ns. 3. The outputs are measured one at a time with one input transition per measurement. FIGURE 4. Test circuit and switching waveforms. Provided by IHSNot for
