1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED B Change VIL, input voltage range, tp CLOCK, tp CLEAR , CLR , PR inactive setup time, IO, ICCL, ICCZ, IIL, and propagation delay times. Remove vendor, CAGE 01295 from device 02. Remove vendor, CAGE 04713 from drawing. Convert to military drawing fo
2、rmat. 87-10-26 Michael A. Frye C Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 02-08-08 Raymond Monnin D Update to reflect latest changes in format and requirements. Correct paragraph in 3.5. Editorial changes throughout. les 05-05-31 Raymond Monnin
3、THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY David W. Queenan DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. D
4、iCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED LOW-POWER SCHOTTKY TTL, FLIP-FLOPS, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 84-05-11 MONOLITHIC SI
5、LICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 84010 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E359-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 432
6、18-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the
7、 following example: 84010 01 K XDrawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function01 54ALS874 Dual 4-bit D-type flip-flop with clear and three st
8、ate outputs 02 54ALS876 Dual 4-bit D-type flip-flop with preset and three state inverted outputs 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package styleK GDFP2-F24 or CDFP3-F24 24 flat L GDIP3-T24 or CDIP4
9、-T24 24 dual-in-line 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . -0.5 V dc to +7.0 V dc Input voltage range -1.2 V dc at -18 mA to +7.0 V dc Storage temperature range -65C to +150C
10、Maximum power dissipation (PD) 1/ 22 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc minimum to +5.5 V dc maximum Minimum high
11、level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) 0.7 V dc Case operating temperature range (TC) . -55C to +125C Width of CLOCK pulse (tpCLOCK) . 20 ns _ 1/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short-circuit test; e.g., IO.
12、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 Width of CLEAR pulse (tp CLEAR) : Device type 01 . 15 n
13、s Width of PRESET pulse (tpPRESET ) : Device type 02 . 10 ns Data setup time . 15 ns CLR or PR inactive state setup time : Device type 01 15 ns Device type 02 10 ns Data hold time (tpHOLD) . 4 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specificat
14、ion, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specifi
15、cation for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (C
16、opies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.2 Order of precedence. In the event of a conflict between the text of
17、this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in ac
18、cordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PR
19、F-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications
20、 shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. Th
21、e design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables.
22、The truth tables shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2
23、.4 Logic diagrams. The logic diagrams shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrica
24、l test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein.
25、 In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in ac
26、cordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted t
27、o DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provi
28、ded with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufactu
29、rers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTE
30、R COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroupsDevice type Limits Unit Min MaxHigh level output voltage VOHVCC= 4.5 V, VIN= 0.7 V or
31、2.0 V, IOH= -1.0 mA 1, 2, 3 All 2.4 V Low level output voltage VOLVCC= 4.5 V, IOL= 12 mA, VIN= 0.7 V or 2.0 V 1, 2, 3 All 0.4 V Input clamp voltage VIC VCC = 4.5 V, TC = +25C, IIN= -18 mA 1, 2, 3 All -1.5 V Low level input current IIL1VCC= 5.5 V, VIN= 0.4 V 1, 2, 3 All -200 A High level input curren
32、t IIH1VCC= 5.5 V, VIN= 2.7 V, 1, 2, 3 All 20 A IH2VCC= 5.5 V, VIN= 7.0 V, 100 Output current IOVCC= 5.5 V, VOUT= 2.25 V 1/ 1, 2, 3 All -15 -112 mA Output current, high level, outputs OFF IOZHVCC= 5.5 V, VOUT= 2.7 V 1, 2, 3 All 20 A Output current, low level, outputs OFF IOZLVCC= 5.5 V, VOUT= 0.4 V 1
33、, 2, 3 All -20 A Supply current, ICCHVCC= 5.5 V, VIN= 0 V 1, 2, 3 01 21 mA outputs high 02 21 Supply current, ICCLVCC= 5.5 V, VIN= 0 V 1, 2, 3 01 30 mA outputs low VCC= 5.5 V, VIN= 5.0 V 02 29 Supply current ICCZVCC= 5.5 V, VOC= 5.0 V 1, 2, 3 All 32 mA outputs disabled Maximum clock frequency fMAX V
34、CC = 5.0 V, CL = 50 pF 10%, 9, 10, 11 All 25 MHz RL = 500 Propagation delay time, high tPHL1VCC= 5.0 V, 9, 10, 11 All 4 23 ns to low, CLR or PR to output CL = 50 pF 10%, RL= 500 5% Propagation delay time, CLK tPLH29, 10, 11 All 4 18 ns to output PHL29, 10, 11 All 4 16 ns See footnotes at end of tabl
35、e. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Cont
36、inued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroupsDevice type Limits Unit Min MaxOutput enable time tPZLVCC= 5.0 V, 9, 10, 11 All 4 21 ns CL= 50 pF 10%, PZH RL = 500 5% 9, 10, 11 All 4 24 ns Output disable time tPLZ9, 10, 11 All 3 22 ns PHZ9, 10, 11 All 2 15 ns
37、1/ The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY
38、 CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device types 01 01 02 02 Case outlines K, L 3 K, L 3 Terminal number Terminal symbols Terminal symbols 1 1 CLR NC 1 PR NC 2 1 OC 1 CLR 1 OC 1 PR 3 1D11 OC 1D1 1 OC 4 1D2 1D1 1D2 1D15 1D3 1D2 1D3 1D2 6 1D4 1D3 1
39、D4 1D37 2D1 1D4 2D1 1D4 8 2D2 NC 2D2 NC9 2D3 2D1 2D3 2D1 10 2D4 2D2 2D4 2D211 2 OC 2D3 2 OC 2D3 12 GND 2D4 GND 2D4 13 2 CLR 2 OC 2 PR 2 OC 14 2CLK GND 2CLK GND15 2Q4 NC 2 Q4 NC 16 2Q32 CLR 2 Q3 2 PR 17 2Q2 2CLK2 Q2 2CLK 18 2Q1 2Q4 2 Q1 2Q4 19 1Q4 2Q31 Q4 2Q3 20 1Q3 2Q2 1 Q3 2Q2 21 1Q2 2Q11 Q2 2Q1 22
40、 1Q1 NC 1 Q1 NC 23 1CLK 1Q4 1CLK1 Q4 24 VCC1Q3 VCC1 Q3 25 - - - 1Q2 - - - 1 Q2 26 - - - 1Q1 - - - 1 Q1 27 - - - 1CLK - - - 1CLK 28 - - - VCC- - - VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT
41、 DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01CLEAR CLOCK OUTPUT CONTROL OUTPUT CLR D CLK OC Q X X X H Z L X X L LH H L H H L L LH X L L Q0H = High level (steady-state) L = Low level (steady-state) X = Irre
42、levant = Transition from low to high level Q0= The level of Q before the indicated steady-state input conditions were established Z = High impedance state Device type 02 PRESET CLOCK OUTPUT CONTROL OUTPUT PR D CLK OC Q X X X H Z L X X L LH H L L H L L HH X L LQ0H = High level (steady-state) L = Low
43、level (steady-state) X = Irrelevant = Transition from low to high level Q0= The level of Q before the indicated steady-state input conditions were established Z = High impedance state FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH
44、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Device type 01FIGURE 3. Logic diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
45、MICROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 Device type 02FIGURE 3. Logic diagrams - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI
46、CROCIRCUIT DRAWING SIZE A 84010 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening sha
47、ll be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by th
48、e manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of
