1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE 27014 for 012X. Editorial changes throughout. Change drawing CAGE code from 14933 to 67268. - mbk 89-01-13 Michael A. Frye B Update boilerplate to MIL-PRF-38535 requirements. jak 01-10-18 Thomas M. Hess C Update boilerplate to MIL
2、-PRF-38535 requirements. - LTG 07-11-28 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-07-25 Thomas M. Hess CURRENT CAGE CODE IS 67268 REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PR
3、EPARED BY Jeffery Tunstall DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Nelson A. Hauck MICR
4、OCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON DRAWING APPROVAL DATE 86-07-02 REVISION LEVEL D SIZE A CAGE CODE 14933 5962-85153 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E503-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without licens
5、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance wi
6、th MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-85153 01 C A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function
7、as follows: Device type Generic number Circuit function 01 54HC73 Dual J-K flip-flop with reset 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-line 2 CQCC1-
8、N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+0.5 V dc DC output voltage . -0.5 V dc to VCC+0.5 V dc Clamp
9、diode current (IIK, IOK) . 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD
10、-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns 1/ Stresses above the abs
11、olute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for
12、ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Minimum setup time, J or K to cloc
13、k (ts): TC= +25C VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C and +125C VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum recovery time, reset to clock (trec): TC= +25C VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C and +125C VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns
14、 VCC= 6.0 V 26 ns Minimum clock pulse width (tw1): TC= +25C VCC= 2.0 V 90 ns VCC= 4.5 V 18 ns VCC= 6.0 V 15 ns TC= -55C and +125C VCC= 2.0 V 135 ns VCC= 4.5 V 27 ns VCC= 6.0 V 23 ns Minimum reset pulse width (tw2): TC= +25C VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C and +125C VCC=
15、2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum hold time, clock to J or K (tH): TC= +25C VCC= 2.0 V 25 ns VCC= 4.5 V 5 ns VCC= 6.0 V 5 ns TC= -55C and +125C VCC= 2.0 V 40 ns VCC= 4.5 V 8 ns VCC= 6.0 V 7 ns Maximum frequency (fMAX): TC= +25C VCC= 2.0 V 5.4 MHz VCC= 4.5 V 27 MHz VCC= 6.0 V 32
16、MHz TC= -55C and +125C VCC= 2.0 V 3.6 MHz VCC= 4.5 V 18 MHz VCC= 6.0 V 21 MHz Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSC
17、C FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solici
18、tation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF
19、 DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 191
20、11-5094). 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Des
21、cription of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-2107). 2.3 Order of precedence. In the event of
22、 a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual
23、item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted tran
24、sitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirem
25、ents herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construct
26、ion, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on
27、figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for Res
28、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the el
29、ectrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in ta
30、ble I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the
31、manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certificat
32、ion mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of complian
33、ce submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-
34、38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and M
35、aritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without
36、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgrou
37、ps Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 1, 2, 3 4.4 VCC= 6.0 V 1, 2, 3 5.9 VIN= VIHor VILIOH= -4.0 mA VCC= 4.5 V 1, 2, 3 3.7 VIN= VIHor VILIOH= -5.2 mA VCC= 6.0 V 1, 2, 3 5.2 Low-level output voltage VOLVIN= VIHor VILIOL= +20 A
38、 VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 1, 2, 3 0.1 VCC= 6.0 V 1, 2, 3 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 1, 2, 3 0.4 VIN= VIHor VILIOL= +5.2 mA VCC= 6.0 V 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V
39、1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent current ICCVIN= VCCor GND VCC= 6.0 V 1, 2, 3 80 A Input leakage current IINVIN= VCCor GND VCC= 6.0 V 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 Propagation delay, time, mCP to mQ or mQ
40、 tPLH1, tPHL13/ CL= 50 pF See figure 4 VCC= 2.0 V 9 170 ns 10, 11 255 VCC= 4.5 V 9 34 10, 11 51 VCC= 6.0 V 9 29 10, 11 43 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 D
41、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay, time, mR to mQ or
42、mQ tPLH2, tPHL23/ CL= 50 pF See figure 4 VCC= 2.0 V 9 155 ns 10, 11 235 VCC= 4.5 V 9 31 10, 11 47 VCC= 6.0 V 9 26 10, 11 40 Transition time, output rise and fall tTHL, tTLH4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 75 ns 10, 11 110 VCC= 4.5 V 9 15 10, 11 22 VCC= 6.0 V 9 13 10, 11 19 1/ For a power suppl
43、y of 5.0 V 10% the worst case output voltage (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designed with this supply. Worst case VINand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, a
44、nd IOZ) occur for CMOS at the higher voltage so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 40 pF, determines the no load dynamic power consumption, PD= CPD VCC2 f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ VIHand VILtests are not re
45、quired if applied as a forcing function for VOHor VOL. 3/ Propagation delay times at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the limits specified in table I. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided by
46、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines C 2 Terminal number Terminal symbol 1 1CP
47、NC 2 1R 1CP 3 1K 1R 4 VCC1K 5 2CP NC 6 2R VCC7 2J NC 8 2Q 2CP 9 2Q 2R 10 2K 2J 11 GND NC 12 1Q 2Q 13 1Q 2Q 14 1J 2K 15 - - - NC 16 - - - GND 17 - - - NC 18 - - - 1Q 19 - - - 1Q 20 - - - 1J NC = No internal connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or net
48、working permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-85153 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Inputs Output mR mCP mJ mK mQ mQ L X X X L H H L L No change H L H L H H H L H L H H H Toggle H L X X No change H H X X No change H X X No change H = High voltage level L = Low voltage level X = Irrelevant = Low-to-high transition of the clock = High-to-low transition of the clock FIGURE 2. Truth table. FIGUR
