1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Convert to military drawing format. Add vendors CAGE 27014 and 18714.Changed min. hold times, prop delay times and terminal connections for case outline 2. Editorial changes throughout. - jt 86-09-12 Nelson A. Hauck B Update boilerplate to MIL-PR
2、F-38535 requirements. jak 01-11-26 Thomas M. HessC Made change to paragraph 3.5. Update boilerplate to MIL-PRF-38535 requirements. LTG 05-01-24 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-08-25 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV
3、 SHET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Jeffery Tunstall DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND
4、AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, 8-BIT ADDRESSABLE LATCH, MONOLITHIC SILICON DRAWING APPROVAL DATE 85-11-12 REVISION LEVEL D SIZE A CAGE CODE 14933 85519 SHEET 1 OF 13 DSCC FORM 2233 APR 97 596
5、2-E480-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requ
6、irements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 85519 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(s
7、ee 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC259 8-Bit addressable latch 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designato
8、r Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5
9、 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+0.5 V dc DC output voltage . -0.5 V dc to VCC+0.5 V dc Clamp diode current. 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 4
10、/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and a
11、ffect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSN
12、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6
13、.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns Minimum setup time, data to address before G (tS): TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C/+125C: VCC= 2.0 V 150
14、 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum hold time, data to address after G (th): TC= +25C: VCC= 2.0 V 25 ns VCC= 4.5 V 5 ns VCC= 6.0 V 5 ns TC= -55C/+125C: VCC= 2.0 V 40 ns VCC= 4.5 V 8 ns VCC= 6.0 V 7 ns Minimum pulse width, CLR or G (tW): TC= +25C: VCC= 2.0 V 80 ns VCC= 4.5 V 16 ns VCC= 6.0
15、V 14 ns TC= -55C/+125C: VCC= 2.0 V 120 ns VCC= 4.5 V 24 ns VCC= 6.0 V 20 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM
16、2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation
17、or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENS
18、E HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia,
19、 PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No
20、. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence
21、. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements
22、. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has
23、been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modification
24、s to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2
25、Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall
26、be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION L
27、EVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specifie
28、d herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are
29、 described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certification/compliance mark. A comp
30、liance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compli
31、ance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the
32、manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of
33、 change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable
34、required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 R
35、EVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 4.4 V
36、CC= 6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC= 4.5 V 1, 2, 3 3.7 VIN= VIHor VILIOH= -5.2 mA VCC= 6.0 V 1, 2, 3 5.2 Low-level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 1, 2, 3 0.4 VIN= VIHor VILIOL= +5.2 mA V
37、CC= 6.0 V 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent current ICCVIN= VCCor GND VCC= 6.0
38、V 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND VCC= 6.0 V 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 Propagation delay time, data to Qn tPLH1, tPHL13/ CL= 50 pF See figure 4 VCC= 2.0 V 9 185 ns 10, 11 280 VCC= 4.5 V 9 3710, 11 56 VCC= 6.0 V 9 3110, 11 48 See footnotes at end of table. Prov
39、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Sy
40、mbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay time, address to Qn tPLH2, tPHL23/ CL= 50 pF See figure 4 VCC= 2.0 V 9 215 ns 10, 11 325 VCC= 4.5 V 9 43 10, 11 65 VCC= 6.0 V 9 37 10, 11 55 Propagation delay time, G to Qn tPHL3,
41、 tPLH33/ CL= 50 pF See figure 4 VCC= 2.0 V 9 200 ns 10, 11 300 VCC= 4.5 V 9 40 10, 11 60 VCC= 6.0 V 9 34 10, 11 51 Propagation delay time, CLR to Qn tPHL43/ CL= 50 pF See figure 4 VCC= 2.0 V 9 155 ns 10, 11 235 VCC= 4.5 V 9 31 10, 11 47 VCC= 6.0 V 9 26 10, 11 40 Transition time, high-to-low, low-to-
42、high tTHL, tTLH4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 75 ns 10, 11 110 VCC= 4.5 V 9 15 10, 11 22 VCC= 6.0 V 9 13 10, 11 19 1/ For a power supply of 5.0 V 10% the worst case output voltage (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst
43、 case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the and 6.0 V values should be used. Power dissipation capacitance (CPD), typically 80 pF, determines t
44、he no load dynamic power consumption, PD= CPD VCC2 f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ Test not required if applied as a forcing function for VOHor VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified limits in t
45、able I. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-399
46、0 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal number Terminal symbol 1 S0 NC 2 S1 S03 S2 S1 4 Q0 S2 5 Q1 Q0 6 Q2 NC 7 Q3 Q1 8 GND Q2 9 Q4 Q3 10 Q5 GND 11 Q6 NC 12 Q7 Q4 13 D Q5 14G Q6 15 CLR Q7 16 VCCNC 17 D 18G 19 CLR 20 VCCNC = No internal connect
47、ion FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Function Table Inputs Output
48、 of addressed latch Each other output Function CLR G H L D Qio Addressable Latch H H Qio Qio Memory L L D L 8-Line Demultiplexer L H L L Clear Latch Selection Table Select inputs Latch addressed S2 S1 S0 L L L L H H H H L L H H L L H H L H L H L H L H 0 1 2 3 4 5 6 7 H = High level voltage L = Low level voltage FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85519 DLA LAND AND MARI
