1、b “- I_ _ DESC-DWG-5528 57 W 7777775 00051110 2 m1 - =7- .,“ DATE LT R DESCRIPTION -b DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. DESC FORM 193 1 - APPROVED Original date of drawing: 19 November 1986 AMSC NIA REV PAGE 1 OF 15 I 4 5962-E8 I I e- Provided by IHSNo
2、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPF 1.1 =, This drawing describes device requirements for class 5 gicrocircuits in accordance Yith 1.3.1 of VIL-STD-893, “Provisions For the use of MIL-STO-583 in conjunction vrith compliant non-JAN devices“, 1.2 P
3、art number, The complete part number shall Se as shown in the following examp1.e: SIZE CODE IDENT. NO. 5962-85528 I I I . DWG NO. x I I I I I +- -Y- I I MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO I i Drawing number Device t pe (1.2.11 4 14933 5962-55528 REV PAGE 2 i I Case outli
4、ne Lead filtish (1.2.2) (3.3) 1.2.1 Device type, The device type shall identify the circuit function as follo:.rs: De v i c e type. Generic nuaber Frequency Circuit o1 82C89 8 MHz CMOS Bus Arbiter 1.2.2 Case outline. The case outline shall be as designated in appendix C of MIL-M-38510, and as fol1 o
5、ws : Outline. letter Case outline ,R 2 0-8 (20-lead, 1/4“ x 1-1/16“), dual -in-1 ine package C-2 (20-terminal, .350“ x .350“), square chip carrier package 1.3 Absolute maximum ratings. Supply voltage (V 1 - - - - - - - - - - - - - - t8.0 v 1/ Input, output or $70 voltage applied - - - - - - GW-0.5 V
6、-to V c+0.5 V i/ Thermal resistance, junction -to case (eje) - - - See 4IL-M-38516, appendix-C Junction tesperature (TJ)- - - - - - - - - - - - +L50*C Temperature under bias - - - - - - - - - - - - - -55C to +125C Storage temperature range- - - - - - - - - - - - -65 to +i5o0c Maximun package power d
7、issipation, (PD) - - - - 1.0 W Lead temperature (soldering, 10 seconds)- - - - - +260C 1.4 Recomnended operating conditions. z/ Supply voltage range (VCC) - - - - - - - - - - - Case operatirig temperature range (Tel- - - - - - 1Yaximuin frequency of operation (fMAx)- - - - - - Setup time, status act
8、ive (t VGH)- - - - - - - - Setup tiine, status inactive tSHCL)- - - - - - - OCLK hi h time (t HC 1 4 - - - - - - - - - - - - Delay t9me, -!o float tBLByH)- - - - - Delay time, ECLK to BUSY float (tBLBYH)- - - - - Input rise time (t,) - - - - - - - - - - - - - Inpgt fall the (tf) - - - - - - - - - -
9、- - - 4.5 V dc to 5.5 Y dc -55C to +125OC o to 9.0 WHz tCLCL -10 ns maximum 3/ tCLCL -10 ns maxilium z/ .65 tBLBL maximm ?/ 35 ns maximua 35 ns aaximum 20 ns maximum 20 os maxiniuli i -1 voltages referenced to Vss. 21 Vce = 4.5 V and 5.5 V. 3J See table I for mininiun limits, Provided by IHSNot for
10、ResaleNo reproduction or networking permitted without license from IHS-,-,- - DESC-DWG-85528 57 7777775 0005LLi2 b .- - b SIZE CODE IDENT. NO. MILITARY DRAWING A 14933 2. 4PPLICABLE DOC1JMEUTS 2.1 Government specification and standard. Unless otiierwise Specified, the following specification ind std
11、ndard, of the issue listed in that issue of the Departinent of Defense Index of Specificationr and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION DWG NO. 5952-55528 MILITARY MIL-M-38510 - Nicrocircuits, General Specification for. ST
12、ANDARD MILITARY DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO MIL-STD-883 - Test Methods and Procedures for Microelectronics. (Copies of the Specification and standard required by manufacturers in connection with specific acquisition functions should be obtained froli the contracting activity or as di
13、rected by the Zontracti ng activity .I references cited herein, the text of this drawing shall take precedence. 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the REV PAGE 3 3. REQUIREMENTS 3.1 Item requirements. T$e individual item requirements shall be in
14、accordance with 1.2.1 of YIL-STO-883, “Provisions for the use of MIL-STD-88J in conjunction with compliant non-JAN devices” and as specified herein. 3.2 Design, constrirction, and physical dimensions. The design, construction, and physical dimensions chal 1 be as specified in MIL-M-38510 and herein.
15、 3.2.1 Terainal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Functional block diagram. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.? herein. 3.J Electrical perforroance characteristics. Unless otherwise specified, the electrical performanc
16、e The functional block diagram shall be as specified on figure 3. characteristics are iii specified in table I and apply over the full recommended case operating temperdture range. 3.4 4arking. narked with the part number listed in 1.2 herein. i.- marked as listed in 6.5 herein. 3.5 Certificate of c
17、ompliance. Drder to be listed as an approved source of supply in 6.5. DESC-ECS prior to listing as an approved source of supply shall state that the manufacturers product neets the requirements of MIL-STD-S8J (see 3.1 herein) and the requirements herein. Marking shall be in accordance with MIL-STD-8
18、83 (see 3.1 herein). The part shall be In addition, the manufacturers part number inay also A certificate OF compliance shall be required from a manufacturer iri The certificate of compliance submitted to I e- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
19、IHS-,-,- BCLK E INIT BREQ BPRO E BPRN - - - - GND E Case 2 5 16 3 LOCK 6 7 14 2 ANYRQCT 8 13 1 AEN 9 12 -J CBRQ 10 11 -J BUSY 15 7 CRQLCK - - m - lg m o) - MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO SIZE GODE IDENT. NO. DWG NO. A 14933 5962-85528 REV PAGE 4 Provided by IHSNot fo
20、r ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85528 57 U 7777775 0005LL14 T U. SIZE CODE IDENT. NO. MILITARY DRAWING A 14933 .+ DWG NO. 5962-85528 . DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO PROCESSOR STATUS REV PAGE 5 I so- LOCK- ;- RESB- CONTROL/ STRAPP
21、ING OPT IONS ANY RQST - i m- ARBITRATION 2 ib STATE GENERATOR 3 CONTROL I 1 f MULTIBUS INTERFACE - - INIT - BCLK - + BREQ - - BPRN - +- BPRO c BUSY -c CBRQ - - MULTIBUS COMMAND S I GNALS I -. SYSTEM SI GNALS - KN - SYSBIRESB +5v GND FIGUKE 2. Functional block diagram. I I I DESC FORM 193A FEB 86 Pro
22、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85528 59 W 9999995 0005I1115 I I 1 I voltage (v013 I VCC = 4.5 v, Ii)H = -lud UA, I (All others) I Test pins 7-8 and 13 I I l I 1 Input leakaye III Vcc = 5.5 V, VIN = or Vcc, I 1, 2, 3 1-1-0 I 1.0
23、 I UA I I current I Test pins 1-6, 9, 14-19 I III I I current ( S I 1, 2, 3 I -lJ I 10 I UA I I I/U leakas, Io I I I I I Vcc = 5.5 V, V N = GrJO or VCC, I m) I Test pins 11-lh I I II I 1 lY I I I I I 10 I UA I Standby supply IIccs I Vcc = 5.5 V, VIN = ti) or Vcc, .I I current I I dutputs open III I
24、I Operating supply IICC,JJ I 1.0 Id/iitiz I Current I I I III I I VC = 5.5 Y, f = 1 r.iliz, Gutputs open, z/ I 1, 2, 3 I MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER / I m to m low I - I CLK to high I I I rntornlow I I I m to miq low I I I I Symbol I Conditions i/ -55C 5 TC 5 +12rC I .CLSK I V
25、CC 4.5 V and 5.5 V 1 7 IVIH 1 7 bLRL i I I I I I IGroup A I Limits I Unit I Isubgroupsl :Un I Max I I I I I I I 19, 10, ill 30 I I nc I I I 13, 10, 111 575 I I ns I I 35 I nc I I II I I - M igy l1I I II 1 I 40 I ns I II I 1 I I I I BLPOH I 19, 10, ill I 25 I ns I 7 I I I I I 7 13, 10, ill I 50 I IK
26、I I I I I I 7 19, 10, ill I 55 I ns I I I I I CLAEH I I 1 I 13, 10, 111 I 40 1 ns I I I I BLAEL I 19, 10, 111 I 60 I ns I 7 I I II I 19 my tPNP0 i tBLYL 1 - hLCBL I I I I Output rise time ItgLOII I VCC = 4.5 V an3 5.5 Y, I/, I 19, 10, ill I 20 I ns I I From 9.8 V to %.O V I I I l I I I I I I I i Out
27、put fall time it0HOL i vCC = 4.5 Y and 5.5 V, l/, is, 10, iii i 12 i ns i I I I Frow 2.0 V to 0.8 V I I II I - 1/ During AC testing, input waveform must switch between VIH+!-).4 Y and VIL-0.4 Y. fall times are driven at lns/V. - 2/ Maximue current defined by CLK or CLK, whichever has the- highest op
28、erating frequency. 31 Tested as follows: f = 1 MHr, VIH = 2.6 Y, VIL = 0.4 V, Load per appropriate AC test circuit, V 4/ Rtyerence paragraph 1.4 for this limit. g/ Both transictionc of tho si na1 apply to parameters with asterisks (*I. 6/ BCLK generates the first db wherein subsequent - through BPRO
29、N. - 7/ Except and m. I?plit rise and Loading is per appropriate AC test circuit (see figure 3). 2 1.5 V, and VOL 5 1.5 V. chariges lower in the chain are generated SIZE CODE IDENT. NO. DWG NO. A 14933 5352-85528 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO REV PAGE 8 DESC FORM 19
30、3A FEE 86 . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85528 57 7777775 0005148 7 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO STATE - CLK - s2, si, so SIZE CODE IDENT. NO. DWG NO. A 14933 5962-85528 REV PAGE 9 CLLLI
31、-4 (SEE NOTE I) SYSBIRESB AEN (SEE NOTE 3 (SEE NOTE 2 1 n kLSRI 4 * CLLL2 I I (SEE NOTE 2) PROCESSOR CLK RELATED II BUS CLK RELATED - BCLK - BREQ 2 - BPRN 2 (WO I) BPRO 2 (BPRN 3) nl Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- DESC-DWG-8552B-59
32、7777775 0005Lq7 7 SIZE CODE IDENT. NO. 14933 MILITARY DRAWING A A.C. Testing: Inputs are driven at VIH *0.4V for a logic “1“ and VIL -0.4Y for a logic “O“. The clock is driven at 4.1 V and 0.4 V. Timing measurements dre made at 1.5 V for both a logic AC testing input, output waveform ll1fl and !loll
33、. OUTPUT INPUT VIH +0.4V VOH VIL -0.4V VOL DWG NO. ,I67 ;p,?:; .- AC testing: Inputs are driven at VIH +0.4 V DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO WOTES: 1. Lock active can occur during any state, as long-as the relationships shown above wtth respect to the CLK.Emaintained. time and can be
34、 asynchronous CRQLCK has no critical timing and is considered an asynclironous input signal. 2. Glitching of SYSB/RESSpecificationc do not exist and qualified military devices tbat will perform the required function are lot available for OEM application. ;his drawing has been qualified for listing o
35、n QPL-35510, the device specified herein will be inactivated and rill riot be used for new design. i1 1 applications. :overed by a contractor-prepared specification or drawing. blhen a niilitary specification exists and the product covered by The qPL-38510 oroduct shall be the preferred item for 6.2
36、 Replaceability. Microcircuits covered by this drawing will renlace the sane generic device 6.3 Comments, Comnnnts on this drawing should be directed t3 DESC-ECS, Dayton, Obi0 45441, or ;el ephone 513-296-5375. SIZE CODE IDENT. NO. DWG NO. MILITARY DRAWING A 14933 5967-85528 DEFENSE ELECTRONLCS SUPP
37、LY CENTER DAYTON, OHIO REV PAGE 12 )ESC FORM 193A FEO 86 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-p . I F 1 DESC-DWG-5528 59 H 7777795 0005152 7 IB I - MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER 6.4 Pin description. I SYMBOL ITYPE I UA
38、ME AYO FUNCTION - I I I I I Power: +5 V supply *io%. I I vcc I I I I I GND I I Ground. SIZE CODE IDENT. NO. DWG NO. a 14933 5962-85525 I I I I DAYTON, OHIO I 1 I - SO,Sl,S21 I 1 Status Input Pins: The status input pins from a processor. The arbiter decodes CLK I I I Clock: From the clock chiD and se
39、rves to establish when bus arbiter actions are I I 1 I these pins to initiate bus request and surrender actions. REV PAGE 13 I I initiated, Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - - DESC-DWG-85528 57 = 7979775 0005153 O 6.4 Pn description,
40、 - Icontinued) I SYMBOL IPYPE I NAAE AND FUNCTION I I 1 I l l E SYSB/ i f i. System Bus/Rssident Bus: An input signal when the arbiter is conffgured in the I I System/Resident Mode (RESB is strapped high) which determines when the niuFti-master t. Sy$em bus is requested and multi-master system bus s
41、urrendering is pernitted. The I signal is intended a originate from a fern of address-mapping circuitry, such as I a decoder or PROM attached to the resident address bus. Signal transitions and I I I glitches are permitted on this pin from 01 of T4 to o1 of T2 of the processor 1 I cycle. During the
42、period from of of T2 to 01 of T4, only clean transitions are I I permitted on this pin (no glitches). I I or miss itr and the multi-master system bus may be requested or surrendered, I I depending upon the state of the glitch. The arbiter requests the multi-master I system bus in the SystenrlResiden
43、t Mode when the state of the SYSB/RESB pin is high I and pernits the bus to be surrendered when this pin is low. I I i U0 i Comon Bus Request: An input signal which instructs the arbiter if there are any i I other arbiters of lower priority requesting the use of the multi-master system bus.1 I I The
44、 pins (open-drain output) of all the Bus Arbiters which surrender to the I I I I I multi-master system bus upon request are connected together. I I I I I I I I I I I 1 I t If a glitch occurs, the arbiter may capture I I I i i I I I I I I I 1 I 1 IT The 3us Arbiter running the current transfer cycle
45、will not itself pull the I line low. Any other arbiter connected to the line can request the multi- I mast-cystem bus. The arbiter presently running the current transfer cycle drops I its BREQ signal and surrenders the bus whenever the proper surrender conditions I exist. Strapping low and ANYRQST h
46、igh allows the multi-master system bus to I be surrendered after each transfer cycle. See the pin definition of ANYRQST, I I i I I O i Bus Clock: The multi-master system bus clock to rqhich all multi-master system bus i 1 1 1 interface signals are synchronized. I I I Bus Request: An active low outpu
47、t signal in the Parallel Prlority Resolving Schemel I I I I I I I Bus Priority In: The active low sjgnal returned to the arbiter to instfiit that/ I I I it may hcqtiire the multi-master system bus on the next falling edge of BCLK. I I I I active indicates to the arbiter that it is the highest priori
48、ty requesting arbiter I I I I presently on the bus. The loss of BPRfi instructs the arbiter that it has lost I I I I priority to a higher priority arbiter. I I I I i U 1 Bus Priority Out: An active low output signalused in the serial priority resolv- I I I , I ng scheme where hpRb is daisy-chained t
49、o BPRW of the next lower priority arbiter, I I i E?J& I /O I Susy: An active low open-drain mirlti-master system bus interface signal used to I I I instruct all the arbiters on the bus when the aulti-master system bus is available.1 1 I I I I I (determined by m) seizes the bus and pulls 83Y low to keep other arbiters off I I 1 of
