1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline 2 (square chip carrier package) for vendor CAGE 27014. 87-05-28 N. A. Hauck B Update boilerplate to MIL-PRF-38535 requirements. jak 01-12-12 Thomas M. Hess C Update boilerplate to MIL-PRF-38535 requirements. - LTG 07-12-17 Thomas
2、 M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-06-21 Thomas M. Hess Current CAGE CODE is 67268 REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Jeffery Tunstall DLA LAND AND MARITI
3、ME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, 4-BIT PARALLEL
4、 SHIFT REGISTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 86-09-30 REVISION LEVEL D SIZE A CAGE CODE 14933 5962-86827 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E424-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
5、A 5962-86827 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identify
6、ing Number (PIN). The complete PIN is as shown in the following example: 5962-86827 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit fun
7、ction 01 54HC195 4-bit parallel shift register 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead fi
8、nish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+0.5 V dc DC input diode current (IIK) 20
9、mA DC output diode current (IOK) . 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Maximum power dissipation (PD) . 500 mW 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +175C S
10、torage temperature range (TSTG) . -65C to +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns 1/ Stresses abo
11、ve the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by I
12、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time, A,
13、 B, C, D, J, or K to clock (tS): TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C/+125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum reset or clock pulse width (tw): TC= +25C: VCC= 2.0 V 80 ns VCC= 4.5 V 16 ns VCC= 6.0 V 14 ns TC= -55C/+125C: VCC= 2.0 V 120 ns V
14、CC= 4.5 V 24 ns VCC= 6.0 V 20 ns Minimum hold time, clock to any input (th): TC= +25C: VCC= 2.0 V 25 ns VCC= 4.5 V 5 ns VCC= 6.0 V 5 ns TC= -55C/+125C: VCC= 2.0 V 40 ns VCC= 4.5 V 8 ns VCC= 6.0 V 7 ns Minimum setup time, shift/load to clock (ts): TC= +25C: VCC= 2.0 V 125 ns VCC= 4.5 V 25 ns VCC= 6.0
15、 V 21 ns TC= -55C/+125C: VCC= 2.0 V 188 ns VCC= 4.5 V 38 ns VCC= 6.0 V 32 ns Minimum recovery time reset inactive to clock (tREC): TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C/+125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Maximum frequency (fMAX): TC= +25C: VCC
16、= 2.0 V 6.0 MHz VCC= 4.5 V 30 MHz VCC= 6.0 V 35 MHz TC= -55C/+125C: VCC= 2.0 V 4.0 MHz VCC= 4.5 V 20 MHz VCC= 6.0 V 24 MHz Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUMBUS,
17、 OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of
18、these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Elec
19、tronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robb
20、ins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY
21、 ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-21
22、07). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIR
23、EMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacture
24、r or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM
25、) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the Q
26、ML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The t
27、erminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUMBU
28、S, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristi
29、cs. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrica
30、l tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number i
31、s not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” sha
32、ll be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
33、(see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certi
34、ficate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and
35、review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo
36、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C
37、1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -5.2 mA VCC= 6.0 V 5.2 Low-level output voltage VOLVIN= VIHor
38、VILIOL= +20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +5.2 mA VCC= 6.0 V 0.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC=
39、4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent current ICCVIN= VCCor GND VCC= 6.0 V 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND VCC= 6.0 V 1, 2, 3 1.0 A Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Functional tests See 4.3.1d 7 Propagation delay time, CP to Qn tPLH1, tPHL13/ CL= 50 pF
40、See figure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 30 10, 11 45 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUM
41、BUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay time, CP to Q3 tPLH2, tPHL23/ CL= 50 pF See
42、 figure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 30 10, 11 45 Propagation delay time, output enable, MR to Qn tPLH33/ CL= 50 pF See figure 4 VCC= 2.0 V 9 150 ns 10, 11 225 VCC= 4.5 V 9 30 10, 11 45 VCC= 6.0 V 9 26 10, 11 38 Propagation delay time, output disable, MR to
43、 Q3 tPHL43/ CL= 50 pF See figure 4 VCC= 2.0 V 9 150 ns 10, 11 225 VCC= 4.5 V 9 30 10, 11 45 VCC= 6.0 V 9 26 10, 11 38 Transition time, High-to-low, Low-to-high tTHL, tTLH4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 75 ns 10, 11 110 VCC= 4.5 V 9 15 10, 11 22 VCC= 6.0 V 9 13 10, 11 19 1/ For a power supply
44、of 5.0 V 10% the worst case output voltage (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VINand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage current (IINand ICC)
45、occur for CMOS at the higher voltage so the 6.0 V values should be used. 2/ VIHand VILtests not required if applied as forcing functions for VOHor VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the limits specified in table I. 4/ Transition times (tTLH, tTHL)
46、shall be guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86827 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM
47、 2234 APR 97 Device type 01 Case outlines E 2 Terminal number Terminal symbol 1 MR NC 2 J MR 3 K J 4 D0 K 5 D1 D0 6 D2 NC 7 D3 D1 8 GND D2 9 PE D3 10 CP GND 11 Q3 NC 12 Q3 PE 13 Q2 CP 14 Q1 Q3 15 Q0 Q3 16 VCCNC 17 - - - Q2 18 - - - Q1 19 - - - Q0 20 - - - VCCNC = No internal connection FIGURE 1. Ter
48、minal connections. Operating modes Inputs Output MR CP PE J K D0 D1 D2 D3 Q0 Q1 Q2 Q3 Q3 Asynchronous reset L X X X X X X X X L L L L H Shift, set first stage H h h h X X X X H q0 q1 q2 q2 Shift, reset first stage H h l l X X X X L q0 q1 q2 q2 Shift, toggle first stage H h h l X X X X q0 q0 q1 q2 q2 Shift, retain first stage H h l h X X X X q0 q0 q1 q2 q2 Parallel load H l X X dn dn dn dn d0 d1 d2 d3 d2 H = High voltage level L = Low voltage level X = Irrelevant = Low to high clock transition l = Low voltage level one set-up time
