1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Correct the voltage levels of the waveforms in figure 5. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 03-05-20 Thomas M. Hess B Rename pin designations in all figures and table I for consistency and to agree
2、 with supplier data. Update boilerplate to MIL-PRF-38535 requirements. - LTG 08-12-17 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Greg A. Pitz CHECKED BY D. A. DiCenzo DEFENSE SUPPLY C
3、ENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-01-12 MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, 8-BIT PARALLEL-I
4、N/SERIAL-OUT SHIFT REGISTER WITH LS TTL COMPATIBLE INPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 14933 5962-86855 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E036-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC
5、IRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, app
6、endix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86855 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type
7、Generic number Circuit function 01 54HCT165 8-bit parallel-in/serial-out shift register with LS TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16
8、 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp
9、diode current 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ . 500 mW Lead temperature (soldering 10 seconds) . 260C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Junction
10、 temperature (TJ) 175C 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENS
11、E SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC). -55C to +125C Input rise or fall time: (tr, tf) VCC= 4.5 V . 0 to 500 ns Mi
12、nimum setup time, serial in to clock, parallel data to shift/load, shift/load to clock, and clock inhibit to clock: (tS) VCC= 4.5 V TC= +25C . 20 ns TC= -55C to +125C . 30 ns Minimum hold time, input from clock: (tH) VCC= 4.5 V TC= +25C . 7.0 ns TC= -55C to +125C . 11 ns Minimum pulse width, clear a
13、nd clock: (tW) VCC= 4.5 V TC= +25C . 20 ns TC= -55C to +125C . 30 ns Maximum clock frequency: (fMAX) VCC= 4.5 V TC= +25C . 27 MHz TC= -55C to +125C . 18 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a pa
14、rt of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STAND
15、ARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available
16、online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this draw
17、ing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE
18、 SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to t
19、his drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying act
20、ivity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described her
21、ein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1
22、Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figur
23、e 3. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3
24、.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in
25、 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator
26、“C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certifica
27、te of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the req
28、uirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to
29、DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the o
30、ption of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical perform
31、ance characteristics. Test Symbol Conditions 1/ -55C TC+125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max IOH= -20 A 4.4 High level output voltage VOHVIN= VIHor VILVCC= 4.5 V IOH= -4.0 mA 1, 2, 3 All 3.7 V IOL= +20 A 1, 2, 3 0.1 1 0.26 Low level
32、output voltage VOLVIN= VIHor VILVCC= 4.5 V IOL= +4.0 mA 2, 3 All 0.4 V High level input voltage VIHVCC= 4.5 V to 5.5 V 1, 2, 3 All 2.0 V Low level input voltage VILVCC= 4.5 V to 5.5 V 1, 2, 3 All 0.8 V 1 0.1 Input leakage current IINVCC= 5.5 V, VIN= VCCor GND 2, 3 All 1.0 A 1 8 Quiescent current ICC
33、 VCC= 5.5 V, VIN= VCCor GND 2, 3 All 160 A 1 360 Additional quiescent supply current ICC 3/ VIN= VCCor GND VCC= 5.5 V 2, 3 All 490 A Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 All 10 pF Functional tests See 4.3.1d 7 All L H TC= +25C 9 35 Propagation delay time, parallel data input D7 to
34、Q7 or 7Q tPHL1, tPLH1VCC= 4.5 V CL= 50 pF See figure 5 TC= -55C, +125C 10, 11 All 53 ns TC= +25C 9 40 Propagation delay time, serial shift , parallel load to Q7 or 7Q tPHL2, tPLH2VCC= 4.5 V CL= 50 pF See figure 5 TC= -55C, +125C 10, 11 All 60 ns TC= +25C 9 40 Propagation delay time, clock (CP) to Q7
35、 or 7Q tPHL3, tPLH3VCC= 4.5 V CL= 50 pF See figure 5 TC= -55C, +125C 10, 11 All 60 ns TC= +25C 9 15 Output transition time 2/ tTHL, tTLHVCC= 4.5 V CL= 50 pF See figure 5 TC= -55C, +125C 10, 11 All 22 ns 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at
36、4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ Transition times, if not tested, shall be guaranteed to the specified parameters. 3/ For dual supply systems theoretical worst case(VIN= 2.4 V and VCC= 5
37、.5 V) specification is 1.8 mA. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case
38、 outline E Terminal number Terminal symbol 1 PL 2 CP 3 D4 4 D5 5 D6 6 D7 7 7Q 8 GND 9 Q7 10 DS 11 D0 12 D1 13 D2 14 D3 15 CE 16 VCCFIGURE 1. Terminal connections. Inputs Qn Register Outputs OPERATING MODE PL CE CP DS D0-D7 Q0Q1 Q6Q7 7QL X X X L L L - L L H Parallel Load L X X X H H H - H H L H L I X
39、 L q0 q5 q66q Serial Shift H L h X H q0 q5q66q Hold Do Nothing H H X X X q0q1 q6q77q H = High voltage level (Steady state) h = High voltage level one setup time prior to the Low-to-High clock transition I = Low voltage level one setup time prior to the Low-to-High clock transition L = Low voltage le
40、vel (Steady state) X = Dont care or Irrelevant = Transition from Low to High level qn= Lower case letters indicate the state of the reference Output Clock transition FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR
41、OCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5
42、962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 FIGURE 4. Functional logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFE
43、NSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 5. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLU
44、MBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 FIGURE 5. Timing waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86855 DEFENSE SUPPLY CENTER COLUMBUS COLUMB
45、US, OHIO 43218-3990 REVISION LEVEL B SHEET 11 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be con
46、ducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be mad
47、e available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test param
48、eters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) 1 Final electrical test parameters (method 5004) 1*, 2, 3, 9 Group A test requirem
