1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE 27014 for case outlines S and 2. Add case outline S. Changes to figure 4, tables I and II and group A inspection. Editorial changes throughout. Change drawing CAGE code to 67268. 89-05-12 M. A. Frye B Delete vendor CAGE 04713. Edi
2、torial changes throughout. 90-09-11 M. A. Frye C Update boilerplate. Add device class V criteria. jak 02-12-18 Thomas M. Hess D Add table III, delta limits. Editorial changes throughout. jak 03-09-11 Thomas M. Hess E Add JEDEC Standard 7-A in paragraphs 2.2 and 4.4.1d. Update boilerplate paragraphs
3、to the current MIL-PRF-38535 requirements. - LTG 10-01-14 Thomas M. Hess CURRENT CAGE CODE IS 67268 REV SHET REV SHET REV STATUS REV E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Greg A. Pitz DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http
4、:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY D. A. DiCenzo APPROVED BY Nelson. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL TRANSPARENT LATCH WITH THREE-STATE OUTPUTS, TTL COMPATIB
5、LE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-04-07 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 14933 5962-86867 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E115-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI
6、ZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choi
7、ce of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 5962 - 868
8、67 01 R A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Case outline (see 1.2.4)Lead finish (see 1.2.5) / /Drawing number For device class V: 5962 - 86867 01 V R A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designa
9、torCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) /Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, a
10、ppendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT373 Octal transparent latch with three-stat
11、e outputs, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators wil
12、l not be included in the PIN and will not be marked on the device. Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and quali
13、fication to MIL-PRF-38535 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). T
14、he case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as speci
15、fied in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+0.5 V dc DC output voltage . -0.5 V dc to VCC+0.5 V dc Clamp diode current (IIK,
16、 IOK) . 20 mA DC output current (per pin) 35 mA DC VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 500 mW 3/ Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temper
17、ature (TJ) +175C 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Input voltage (VIN) 0 V dc to VCCOutput voltage (VOUT) . 0 V dc to VCC Case operating temperature (TC) . -55C to +125C Input rise or fall
18、time (tr, tf) (VCC= 4.5 V) 0 to 500 ns Minimum setup time, data to LATCH ENABLE (ts): TC= +25C, VCC= 4.5 V 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Minimum LATCH ENABLE pulse width (tw): TC= +25C, VCC= 4.5 V 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Minimum hold time, data to LATCH ENABLE (th):
19、 TC= +25C, VCC= 4.5 V 10 ns TC= -55C to +125C, VCC= 4.5 V . 20 ns 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are reference
20、d to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC
21、 FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicit
22、ation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF
23、DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philade
24、lphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 7-A
25、- Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict b
26、etween the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirem
27、ents for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements
28、 for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device class
29、es Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on
30、figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-
31、,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance cha
32、racteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are de
33、fined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962
34、-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The cert
35、ification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required fro
36、m a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate
37、 of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and h
38、erein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. Fo
39、r device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain th
40、e option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit gr
41、oup number 38 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TAB
42、LE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VIL, VIH= 2.0 V VCC= 4.5 V, VIL= 0.8 V IOH= -20 A 1, 2, 3 4.4 V VIN= VIHor VIL, VIH= 2.0 V VCC= 4.5 V, V
43、IL= 0.8 V IOH= -6.0 mA 1, 2, 3 3.7 Low-level output voltage VOLVIN= VIHor VIL, VIH= 2.0 V VCC= 4.5 V, VIL= 0.8 V IOL= +20 A 1, 2, 3 0.1 V VIN= VIHor VIL, VIH= 2.0 V VCC= 4.5 V, VIL= 0.8 V IOL= +6.0 mA 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 4.5 V 1, 2, 3 2.0 V Low-level input voltage VIL2/ V
44、CC= 4.5 V 1, 2, 3 0.8 V Quiescent current ICCVIN= VCCor GND VCC= 5.5 V IOUT= 0.0 A 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND VCC= 5.5 V 1, 2, 3 1.0 A Three-state output current IOZVIN= 2.0 V or 0.8 V VCC= 5.5 V VOUT= VCCor GND 1, 2, 3 10 A Additional quiescent supply current ICCAny one i
45、nput VIN = 2.4 V or 0.5 V Other inputs VIN= VCCor GND VCC= 5.5 V, IOUT= 0.0 A 1, 2, 3 3.0 mA Input capacitance CINVIN= 0.0 V, TC= +25C See 4.4.1d 4 10 pF Output capacitance COUTTC= +25C See 4.4.1d 4 20 pF Functional tests See 4.4.1b 7, 8 Propagation delay time, Dn to Qn tPLH1, tPHL13/ VCC= 5.0 V CL=
46、 50 pF See figure 4 9 35 ns 10, 11 53 Propagation delay time, LE to Qn tPHL2, tPLH23/ 9 35 ns 10, 11 53 Propagation delay time, output disable, OE to Qn tPHZ, tPLZ3/ 9 35 ns 10, 11 53 Propagation delay time, output enable, OE to Qn tPZH, tPZL3/ 9 35 ns 10, 11 53 Transition time, high-to-low, low-to-
47、high tTHL, tTLH4/ 9 12 ns 10, 11 18 See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86867 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FO
48、RM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage and so the 5.5 V values should be used. Power dissipation capacitance (CPD), typically 40 pF, determines the no load dynamic power consumption, PD= CPD VCC2f+ICC VCC; and the no load dynamic current consumpti
