1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Made changes to 3.3, 4.2, 4.3.1, and 4.3.2. Made changes to table I. Editorial changes throughout. 90-03-08 M. A. Frye B Add device type 07. Add vendors CAGEs 1ES66 and 54186. Editorial changes throughout. 93-01-22 M. A. Frye C Update boilerplate
2、 and make editorial changes throughout. - ro 98-07-06 Raymond Monnin D Update drawing to current requirements. Editorial changes throughout. drw 04-01-07 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV D D D SHET 15 16 17 REV STATUS REV D D D D D D D D D D D D
3、 D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A
4、. Frye MICROCIRCUIT, CMOS, 12-BIT MULTIPLYING DIGITAL TO ANALOG CONVERTER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-01-28 MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-87702 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E557-03 DISTRIBUTION STATEMENT A
5、. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 2 DSCC FORM 2234
6、APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87702 01 R A Drawing nu
7、mber Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 7545S CMOS 12-bit buffered DAC 02 7545T CMOS 12-bit buffered DAC 03 7545U CMOS 12-bit buffered D
8、AC 04 7545AU CMOS 12-bit buffered DAC 05 7545B CMOS 12-bit buffered DAC 06 7545A CMOS 12-bit buffered DAC 07 7545S CMOS 12-bit buffered DAC 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T
9、20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VDD) +5 V dc to +15 V dc VREFto GND . -0.3 V dc to +17 V dc Digital input voltage to DGND -
10、0.3 V dc to VDDVRFB, VREFto DGND . 25 V dc V pin 1 to DGND -0.3 V dc to VDDAGND to DGND . -0.3 V dc to VDDPower dissipation (PD): Up to +75C 450 mW Derates above +75C . 6 mW/C Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance junction-to-case (
11、JC) . See MIL-STD-1835 Thermal resistance junction-to-ambient (JA): Case R +120C/W Case 2 . +120C/W Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Operating ambient temperature range (TA) . -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted with
12、out license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and
13、 handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION
14、DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 -
15、List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Ord
16、er of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 I
17、tem requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manuf
18、acturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may m
19、ake modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow opti
20、on is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical
21、 dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3
22、 Mode selection. The mode selection shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and s
23、hall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-385
24、35, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the opt
25、ion of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance w
26、ith MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA
27、prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with e
28、ach lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers f
29、acility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. S
30、creening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C or D. The test circuit shall be maint
31、ained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 10
32、15 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. Optional subgroup 12 is used for grading and part sel
33、ection at +25C. It is not included in PDA. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I
34、. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxResolution RES VDD= +5 V 1, 2, 3 All 12 Bits VDD= +15 V 12 Relative accuracy RA VDD= +5 V 1, 2, 3 01, 07 2 LSB 1 02 2 2, 3 1 VDD= +5 V, TA= +2
35、5C 2/ 12 02 1 VDD= +5 V 1 03, 04 2 05, 06 0.5 2, 3 03, 04, 05, 06 0.5 VDD= +5 V, TA= +25C 2/ 12 03, 04, 05, 06 0.5 VDD= +15 V 1, 2, 3 01, 07 2 1 02 2 2, 3 1 VDD= +15 V, TA= +25C 2/ 12 02 1 VDD= +15 V 1 03, 04 2 05, 06 0.5 VDD= +15 V 2/ 2, 3 03, 04, 05, 06 0.5 12 0.5 See footnotes at end of table. Pr
36、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - co
37、ntinued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxDifferential nonlinearity DNL VDD= +5 V, 10-bit monotonic 1, 2, 3 01, 07 4 LSB VDD= +5 V, 12-bit monotonic 1 02, 03, 04 4 05, 06 1 VDD= +5 V, 2/ 12-bit monotonic 2, 3 1 12 02,
38、 03, 04, 05, 06 1 VDD= +15 V, 10-bit monotonic 1, 2, 3 01, 07 4 VDD= +15 V, 12-bit monotonic 1 02, 03, 04 4 05, 06 1 VDD= +15 V, 2/ 12-bit monotonic 2, 3 1 12 02, 03, 04, 05, 06 1 Power supply rejection PSRR VDD= +5 V, VDD= 5 % 1 .015 % / % 2, 3 01, 02, 03, 04, 07 .03 1 05, 06 .002 2, 3 .004 VDD= +1
39、5 V, VDD= 5 % 1 .01 2, 3 01, 02, 03, 04, 07 .02 1 05, 06 .002 2, 3 .004 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216
40、-5000 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxGain error 3/ AE VDD= +5 V, 1, 2, 3 01, 07 20 LSB DAC register loaded
41、with 1111 1111 1111 1 02 20 2, 3 10 VDD= +5 V, TA= +25C 2/ 12 02 10 DAC register loaded with 1111 1111 1111 VDD= +5 V, 1 03 20 DAC register loaded with 1111 1111 1111 05 3 2, 3 03 6 05 4 VDD= +5 V, TA= +25C 2/ 12 03 5 DAC register loaded with 1111 1111 1111 05 3 VDD= +5 V, 1 04 20 DAC register loade
42、d with 1111 1111 1111 06 1 2, 3 04, 06 2 VDD= +5 V, TA= +25C 2/ DAC register loaded with 1111 1111 1111 12 04, 06 1 VDD= +15 V, 1, 2, 3 01, 07 25 DAC register loaded with 1111 1111 1111 1 02 25 2, 3 15 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitte
43、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise
44、 specified Group A subgroups Device type Limits Unit Min MaxGain error 3/ AE VDD= +15 V, TA= +25C, DAC register loaded with 1111 1111 1111 2/ 12 02 15 LSB VDD= +15 V, 1 03 25 DAC register loaded with 1111 1111 1111 05 3 2, 3 03 10 05 4 VDD= +15 V, TA= +25C, 12 03 10 DAC register loaded with 1111 111
45、1 1111 2/ 05 3 VDD= +15 V, 1 04 25 DAC register loaded with 1111 1111 1111 06 1 2, 3 04 7 06 2 VDD= +15 V, TA= +25C, 12 04 6 DAC register loaded with 1111 1111 1111 2/ 06 1 Output leakage current Pin 1 IOUT1VDD= +5 V, DB0 to DB11 = 0 V, 1 All 10 nA WR, CS = 0 V 2, 3 200 VDD= +15 V, DB0 to DB11 = 0 V
46、, 1 All 10 WR, CS = 0 V 2, 3 200 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87702 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 9 DSCC FOR
47、M 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxReferenced input resistance, pin 19 to ground RINVDD= +5 V 1, 2, 3 01, 02, 03, 04, 07 7 25 k 05, 06 7 15 VDD=
48、 +15 V 1, 2, 3 01, 02, 03, 04, 07 7 25 05, 06 7 15 Digital input high voltage VIHVDD= +5 V 1, 2, 3 All 2.4 V VDD= +15 V 13.5 Digital input low voltage VILVDD= +5 V 1, 2, 3 All 0.8 V VDD= +15 V 1.5 Digital input leakage current IINVDD= +5 V 1 All 1 A 2, 3 10 VDD= +15 V 1 1 2, 3 10 Supply current from VDDIDDVDD= +5 V, all digital inputs VILor VIH1, 2, 3 All 2 mA VDD= +15 V, all digital inputs VILor VIH2 VDD= +5 V, all digital in
