1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I, change tH on page 6. Editorial changes throughout. 88-11-10 M. A. Frye B Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 05-02-28 Raymond Monnin C Update drawing as part of 5 year review. -
2、 jt 11-09-12 C. SAFFLE THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV C SHEET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandma
3、ritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Ray Monnin APPROVED BY Michael A. Frye MICROCIRCUITS, DIGITAL, QUAD BUS TRANSCEIVER, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-11-18 AMSC N/A REVIS
4、ION LEVEL C SIZE A CAGE CODE 67268 5962-87707 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E498-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE
5、VEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
6、 5962-87707 01 R X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 2907 Quad bus transceiver with interface logic and 2.0 V input
7、receiver threshold 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line S GDFP2-F20 or CDFP3-F20 20 flat 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish
8、. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range . -1.5 V dc to +7.0 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ 1.1 W Lead temperature (soldering, 10 sec
9、onds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +150C DC input current -30 mA to +5.0 mA DC output current into outputs (except bus) +30 mA DC output current into bus 200 mA _ 1/ Maximum power dissipation is defined as VCCx ICC, and must withstand t
10、he added PDdue to short-circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recomm
11、ended operating conditions. Supply voltage (VCC) +4.5 V dc to +5.5 V dc Driver characteristics: High level input voltage (VIH) +2.0 V dc minimum Low level input voltage (VIL) +0.7 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification,
12、 standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 -
13、Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings
14、. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a confl
15、ict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item req
16、uirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional
17、 certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements her
18、ein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for Resale
19、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physica
20、l dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specifie
21、d on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching test circuits and waveforms. The switching test circuits and waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electr
22、ical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table
23、I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manu
24、facturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification
25、mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance s
26、ubmitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-3853
27、5, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Marit
28、imes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice
29、nse from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits U
30、nit unless otherwise specified Min Max BUS INPUT/OUTPUT PARAMETERS Output low voltage bus VOLVCC= 4.5 V, VIN= VILor VIHIOL= 40 mA 1, 2, 3 All 0.5 V IOL= 70 mA 0.7 IOL= 100 mA 0.8 Input high voltage (receiver) VTHBus enable = 2.4 V 1/ 1, 2, 3 All 2.4 V Input low voltage (receiver) VTLBus enable = 2.4
31、 V 1/ 1, 2, 3 All 1.5 V Bus leakage current IOVCC= 5.5 V VO= 0.4 V 1, 2, 3 All -50 A VO= 4.5 V 200 A Bus leakage current (power off) IOFFVCC= 0 V, VOUT= 4.5 V 1, 2, 3 All 100 A Input clamp voltage VI C VCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.2 V See footnotes at end of table Provided by IHSNot for Re
32、saleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions
33、-55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max DC PARAMETERS Output high voltage (receiver) VOHVCC= 4.5 V, VIN= VILor VIH, IOH= -1.0 mA 1, 2, 3 All 2.4 V Output high voltage parity VOHVCC= 4.5 V, VIN= VILor VIH, IOH= -660 A 1, 2, 3 All 2.5
34、V Output low voltage (except bus) VOLVCC= 4.5 V, VIN= VILor VIHIOL= 4.0 mA 1, 2, 3 All 0.4 V BE = 2.4 V IOL= 8.0 mA 0.45 IOL= 12.0 mA 0.5 Input clamp voltage VI CVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.2 V Input high current IIH VCC= 5.5 V, VIN= 2.7 V 1, 2, 3 All 20 A Input low current IIL VCC= 5.5 V
35、, VIN= 0.4 V 1, 2, 3 All -0.36 mA Input reverse current IIVCC= 5.5 V, VIN= 5.5 V 1, 2, 3 All 100 A Output short circuit current IOSVCC= 5.5 V 2/ 1, 2, 3 All -12 -65 mA Power supply current ICCVCC= 5.5 V, BE = OE = 3.0 V, All other inputs = GND 1, 2, 3 All 110 m Off-state output current IOVCC= 5.5 V
36、VO= 2.4 V 1, 2, 3 All 20 A (receiver outputs) VO= 0.4 V -20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL
37、C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max AC PARAMETERS Propagation delay driver clock (DRCP) to bus tPLHCL= 50 pF, RL2
38、= 50 See figure 4 9, 10, 11 All 40 ns Propagation delay driver clock (DRCP) to bus tPHL9, 10, 11 All 40 ns Bus enable to bus tPLH9, 10, 11 All 26 ns Bus enable to bus tPHL9, 10, 11 All 26 ns A data inputs setup tSSee figure 4 9, 10, 11 All 18 ns A data inputs hold tH9, 10, 11 All 10 ns Clock pulse w
39、idth (High) tPWH 9, 10, 11 All 28 ns Propagation delay bus to receiver output (latch enabled) tPLHCL= 15 pF, RL1= 5.0 k, RL2= 2.0 k See figure 4 9, 10, 11 All 37 ns Propagation delay bus to receiver output (latch enabled) tPHL9, 10, 11 All 37 ns Propagation delay latch enable to receiver output tPLH
40、9, 10, 11 All 37 ns Propagation delay latch enable to receiver output tPHL9, 10, 11 All 37 ns Bus to latch enable tSSee figure 4 9, 10, 11 All 21 ns Bus to latch enable tH9, 10, 11 All 7 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without li
41、cense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device
42、 type Limits Unit unless otherwise specified Min Max AC PARAMETERS Continued Propagation delay A data to odd parity out (driver enabled) tPLHCL= 15 pF, RL2= 2.0 See figure 4 9, 10, 11 All 40 ns Propagation delay A data to odd parity out (driver enabled) tPHL9, 10, 11 All 40 ns Propagation delay bus
43、to odd parity out (driver inhibit) tPLH9, 10, 11 All 40 ns Propagation delay bus to odd parity out (driver inhibit) tPHL9, 10, 11 All 40 ns Propagation delay latch enable to odd parity output tPLH9, 10, 11 All 40 ns Propagation delay latch enable to odd parity output tPHL9, 10, 11 All 40 ns Propagat
44、ion delay output control to output tPZHCL= 15 pF, RL1= 5.0 k, RL2= 2.0 k See figure 4 9, 10, 11 All 28 ns Propagation delay output control to output tPZL9, 10, 11 All 28 ns Propagation delay output control to output tPHZCL= 5 pF, RL1= 5.0 k, RL2= 2.0 k See figure 4 9, 10, 11 All 28 ns Propagation de
45、lay output control to output tPLZ9, 10, 11 All 28 ns 1/ Input thresholds are tested during dc testing and done in combination with other dc parameters. 2/ Not more than one output should be shorted at a time and the duration of the short circuit condition should not exceed one second. Provided by IH
46、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87707 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 Device type 01 Case outlines R and S 2 Terminal number Terminal symbol Te
47、rminal symbol 1 RLE RLE 2 R0R03 A0A04 BUS0BUS05 GND1GND16 BUS1BUS17 A1A18 R1R19 BE BE 10 ODD ODD 11 OE OE 12 R2R213 A2A214 BUS2BUS215 GND2GND216 BUS3BUS317 A3A318 R3R319 DRCP DRCP 20 VCCVCCFIGURE 1. Terminal connections. Internal to device Bus Output Function AiDRCP BE RLEOE DiQiBiRiX X H X X X X H
48、X Driver output disable X X X X H X X X Z Receiver output disable X X H L L X L L H Driver output disable and receive data via Bus input X X H L L X H H L X X X H X X NC X X Latch received data L X X X L X X X Load driver register H X X X H X X X X L X X X NC X X X No driver clock restrictions X H X X X NC X X X X X L X X H X L X Drive Bus H = HIGH voltage level Z = HIGH impedance X = Dont
