1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change to table I, parameter tSCT. Correction to vendor similar part number. Editorial changes throughout. 90-01-08 Michael A. Frye B Changes in accordance with NOR 5962-R088-92. 91-12-13 Michael A. Frye C Boilerplate update, part of 5 year revie
2、w. ksr 10-04-23 Charles F. Saffle The original first page of this drawing has been replaced. REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING
3、 CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, 512 X 8 BIT NONVOLATILE STATIC RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROV
4、AL DATE 88-01-12 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-87712 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E250-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUM
5、BUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete
6、PIN is as shown in the following example: 5962-87712 01 X_ A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 Generic number 2004 2004 Circuit function 512 x 8 bit
7、, nonvolatile static RAM 512 x 8 bit, nonvolatile static RAM Access time 250 ns 300 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 and CDIP2-T28 28 dual-in-line package Y CQCC1-
8、N32 32 rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Temperature under bias - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -65C to +135C Storage temperature- - - - - - - - - - - - -
9、 - - - - - - - - - - - - - - - - - - - - - - - - -65C to +150C Voltage on any pin with respect to ground - - - - - - - - - - - - - - - - - - - - - -1.0 V to +7.0 V dc DC output current - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5.0 mA Lead temperature (soldering, 10
10、seconds)- - - - - - - - - - - - - - - - - - - - - 300C Power dissipation (PD) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.75 W Thermal resistance, junction-to-case (JC)- - - - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Junction temperature (TJ) - - - - - - - - - - -
11、 - - - - - - - - - - - - - - - - - - - - - 200C 1.4 Recommended operating conditions. Supply voltage (VCC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 4.5 V dc to 5.5 V dc Minimum high level input voltage (VIH)- - - - - - - - - - - - - - - - - - - - - - - - +2.3 V dc Maxi
12、mum high level input voltage (VIH) - - - - - - - - - - - - - - - - - - - - - - - +VCC+ 0.5 V dc Minimum low level input voltage (VIL) - - - - - - - - - - - - - - - - - - - - - - - - -0.5 V dc Maximum low level input voltage (VIL) - - - - - - - - - - - - - - - - - - - - - - - - +0.8 V dc Case operati
13、ng temperature range (TC) - - - - - - - - - - - - - - - - - - - - - - - -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LE
14、VEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those ci
15、ted in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlin
16、es. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Bu
17、ilding 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific ex
18、emption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML)
19、 certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as docu
20、mented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-3853
21、5 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified o
22、n figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise sp
23、ecified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgro
24、up are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to s
25、pace limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “
26、Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHI
27、O 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V (Unless otherwise specified) Group A subgroups Device type Limits Unit Min Max Input low voltage VIL1,2,3 01,02 -0.1 0.8 V Input
28、 high voltage VIH1,2,3 01,02 2.0 VCC+ 1.0 V Output low voltage VOLIOL= 2.1 mA 1,2,3 01,02 0.4 V Output high voltage VOHIOH= -400 A 1,2,3 01,02 2.4 V Power supply current (active) ICC1= VIL, II/0= 0 mA, all other inputs = VCC1,2,3 01,02 120 mA Power supply current (standby) ICC2All inputs = VCC, II/0
29、= 0 mA 1,2,3 01,02 90 mA Input capacitance CINVI/0= 0 V, TA= 25C, Frequency = 1 MHz 1/ see 4.3.1c 4 01,02 6 pF Output capacitance COUTVI/0= 0 V, TA= 25C, Frequency = 1 MHz 1/ see 4.3.1c 4 01,02 10 pF Read cycle time tAVAVSee figure 4 2/ 9,10,11 01 250 ns 02 300 Chip enable access time tELDVSee figur
30、e 4 2/ 9,10,11 01 250 ns 02 300 Address access time tAVAQSee figure 4 2/ 9,10,11 01 250 ns 02 300 Output enable access time tOLQVSee figure 4 2/ 9,10,11 01 100 ns 02 150 Chip enable output to low Z tELDXSee figure 4 2/ 9,10,11 01,02 10 ns See footnotes at end of table. Provided by IHSNot for ResaleN
31、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditi
32、ons -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V (Unless otherwise specified) Group A subgroups Device type Limits Unit Min Max Chip enable output to high Z tELDZSee figure 4 2/ 9,10,11 01,02 10 100 ns Output enable output to low Z tOLQXSee figure 4 2/ 9,10,11 01,02 10 ns Output enable output to high Z t
33、OHQZSee figure 4 2/ 9,10,11 01,02 10 100 ns Output hold from address change tAVQXSee figure 4 1/ 2/ 9,10,11 01,02 0 ns Write cycle time tELEHSee figure 5 2/ 9,10,11 01 250 ns 02 300 Chip enable to end of write input tELWHSee figure 5 2/ 9,10,11 01 250 ns 02 300 Address setup time tAVWLSee figure 5 2
34、/ 9,10,11 01,02 0 ns Write pulse width tWLWHSee figure 5 2/ 9,10,11 01 150 ns 02 200 Write recovery time tEHAXSee figure 5 2/ 9,10,11 01,02 0 ns Data valid to end of write cycle tDVWHSee figure 5 2/ 9,10,11 01 150 ns 02 200 Data hold time tWHDXSee figure 5 2/ 9,10,11 01,02 0 ns Write enable to outpu
35、t in high Z tWLQZSee figure 5 2/ 9,10,11 01,02 10 100 ns Output active from end of write cycle tWHQXSee figure 5 2/ 9,10,11 01,02 10 ns Output enable to output in high Z tOHQZSee figure 5 2/ 9,10,11 01,02 10 100 ns Store cycle time tSTCSee figure 6 2/ 9,10,11 01,02 10 ms See footnotes at end of tabl
36、e. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics
37、 Continued. Test Symbol Conditions -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V (Unless otherwise specified) Group A subgroups Device type Limits Unit Min Max Store pulse width tSPSee figure 6 2/ 4/ 9,10,11 01 150 ns 02 200 Nonvolatile enable to output in high Z tNHZSee figure 6 2/ 9,10,11 01,02 100 ns O
38、utput enable from end of store tOESTSee figure 6 2/ 9,10,11 01,02 10 ns Disable to store function tSOESee figure 6 2/ 9,10,11 01,02 20 ns setup time from tNSSee figure 6 2/ 9,10,11 01,02 0 ns Array recall cycle time tRCCSee figure 6 2/ 9,10,11 01,02 5 s Recall pulse width to initiate recall tRCPSee
39、figure 6 2/ 3/ 5/ 9,10,11 01 150 02 200 ns setup to tRWESee figure 6 2/ 9,10,11 01,02 0 ns 1/ Tested initially and after any design or process changes which may affect this parameter, and is guaranteed to the limits specified in table I. 2/ AC test conditions: Input high level VIH= 3.0 V. Input low
40、level VIL= 0.0 V. Input rise/fail times tR= 10 ns. Output voltage high VIH 1.5 V. Output voltage low VIL 1.5 V. Output load CL= 100 pF. Input and output timing levels = 1.5 V. 3/ This device features internal control of the recall cycle time, tRCPis the minimum input pulse width required to initiate
41、 a recall. Once initiated, the recall cycle will have a completion time of tRDVwhich varies. As tRCPis increased above its minimum value, the cycle time tRCCremains constant and tRDVis reduced accordingly until reaching its minimum value. If tRCPis increased further, tRDVremains constant and the ent
42、ire cycle time will increase. 4/ The store pulse width (tSP) is a minimum time that , , and must be LOW simultaneously. To insure data integrity, and must return HIGH after initiation of and throughout the duration (tSTC, 10 ms) of the store operation. During tSTC, and may go LOW providing the host,
43、 access to the other devices in the system. 5/ The recall pulse width (tRCP) is a minimum time that , , and must be LOW simultaneously. To insure data integrity, and must return HIGH after initiation of and throughout the duration (tRCC, 5 s) of the recall operation. During tRCC, and may go LOW prov
44、iding the host, access to the other devices in the system. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87712 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 223
45、4 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall
46、affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8
47、 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. Defense Supply Center Columbus (DSCC), DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable req
48、uired documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under do
