1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Make changes to table I, figure 3, figure 7, and editorial changes throughout. 88-11-16 Michael A. Frye B Remove vendor CAGE number 50364 as a source of supply for device types 09 through 11. Changes to table I and figure 8. Editorial changes thr
2、oughout. 89-10-30 Michael A. Frye C Add device type 12. Update drawing to current requirements. Editorial changes throughout. ksr. 10-03-17 Charles F. Saffle D Changed limits for device types 05 and 07 in Table I tests tOPHand tIPHfrom 30 to 20 ns Min. Added vendor CAGE number 0DKS7 as a source of s
3、upply for device types 01, 03, 05, and 07. glg 12-05-11 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED REV SHEET REV D D D D SHEET 15 16 17 18 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer DE
4、FENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, BIPOLAR, FIRST-IN FIRST-OUT (FIFO), MONOLI
5、THIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-12-17 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-87791 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E275-12 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA
6、RD MICROCIRCUIT DRAWING SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, app
7、endix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87791 01 E_ A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device t
8、ype Generic number 1/ Circuit function 01 1/ 57401 7 MHz 64x4 stand-alone first-in first-out memory 02 57402 7 MHz 64x5 stand-alone first-in first-out memory 03 1/ 57401A 10 MHz 64x4 stand-alone first-in first-out memory 04 57402A 10 MHz 64x5 stand-alone first-in first-out memory 05 1/ C57401 7 MHz
9、64x4 cascadable first-in first-out memory 06 C57402 7 MHz 64x5 cascadable first-in first-out memory 07 1/ C57401A 10 MHz 64x4 cascadable first-in first-out memory 08 C57402A 10 MHz 64x5 cascadable first-in first-out memory 09 57L401D 12 MHz 64x4 stand-alone first-in first-out memory 10 57L402D 12 MH
10、z 64x5 stand-alone first-in first-out memory 11 57L4013D 12 MHz 64x4 stand-alone three-state first-in first-out memory 12 1/ C57401E 16 MHz 64x4 cascadable first-in first-out memory 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptiv
11、e designator Terminals Package style E GDIP1-T16, CDIP2-T16 16 dual-in-line package V GDIP1-T18, CDIP2-T18 18 dual-in-line package 2 CQCC1-N20 20 square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage
12、range- -0.5 V dc to +7 V dc Input voltage range - -1.5 V dc to +7 V dc Storage temperature range - -65C to +150C Lead temperature: Soldering, 5 seconds, E and V outline - +300C Soldering, 10 seconds, 2 outline - +260C Thermal resistance, junction-to-case (JC) 2/ See MIL-STD-1835 Output voltage appli
13、ed range - -0.5 V dc to +5.5 V dc Output sink current - 100 mA 1/ Device types supplied by CAGE 0DKS7 are emulated using CMOS technology to meet the requirements of this drawing. 2/ Heat sinking is recommended to reduce the junction temperature. Provided by IHSNot for ResaleNo reproduction or networ
14、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings Continued. Maximum power dissipation (PD) 3/: Device types 01 and 05 - 880 mW Device
15、 types 02, 03, 06, and 07- 990 mW Device types 04 and 08 - 1.1 W Device types 09, 10, 11, and 12- 660 mW Maximum junction temperature (TJ) - +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) - 4.5 V to 5.5 V Case operating temperature range (TC) - - 55C to +125C Static low level
16、 input voltage (VIL1) - 0.8 V maximum 4/ Static high level input voltage (VIH1) - 2.0 V minimum 4/ AC low level input voltage (VIL2) - 0 V maximum 4/ AC high level input voltage (VIH2) - 3.0 V minimum 4/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following sp
17、ecification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General
18、 Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Draw
19、ings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and th
20、e references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-P
21、RF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be proc
22、essed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect f
23、orm, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3/ Must withstand the added PDdue to short circuit test; e.g. IOS. 4/ Th
24、ese are absolute voltages with respect to the ground pin on the device and include all overshoots due to system or tester noise. Do not attempt to test these values without suitable equipment. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
25、MICROCIRCUIT DRAWING SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.
26、2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Logic diagram. The logic diagram shall be as specified on figure 2. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwis
27、e specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each su
28、bgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due
29、to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with
30、 a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). T
31、he certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in
32、MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Lan
33、d and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection p
34、rocedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015
35、 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applica
36、ble, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer.
37、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symb
38、ol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Input clamp voltage VICVCC= 4.5 V, II= -18.0 mA, 1, 2, 3 All -1.5 V Low level input current IIL1VCC= 5.5 V, VI= 0.45 V, D0 Dn, MR 1, 2, 3 01-08, 12 -0.8 mA IIL2VCC= 5.5 V, VI= 0.4
39、5 V SI, S0 1, 2, 3 01-08, 12 -1.6 mA IILVCC= 5.5 V, VI= 0.45 V 1, 2, 3 9,10,11 -250 A High level input current IIHVCC= 5.5 V, VI= 2.4 V 1, 2, 3 All 50 A Maximum input current IIVCC= 5.5 V, VI= 5.5 V 1, 2, 3 All 1 mA Low level output voltage VOLVCC= 4.5 V, IOL= 8.0 mA, VIL= 0.8 V, VIH= 2.0 V 1, 2, 3
40、01-08, 12 VCC= 4.5 V, IOL= 12.0 mA, O0- On VIL= 0.8 V, VIH= 2.0 V 9,10,11 0.5 V VCC= 4.5 V, IOL= 8.0 mA, VIL= 0.8 V, VIH= 2.0 V IR, OR 9,10,11 High level output voltage VOHVCC= 4.5 V, IOH= -0.9 mA, VIL= 0.8 V, VIH= 2.0 V 1, 2, 3 01-08, 12 VCC= 4.5 V, IOH= -3.0 mA, O0- On VIL= 0.8 V, VIH= 2.0 V 9,10,
41、11 2.4 V VCC= 4.5 V, IOH= -0.9 mA, VIL= 0.8 V, VIH= 2.0 V IR, OR 9,10,11 Output short circuit IOSVCC= 5.5 V, VO= 0 V 1, 2, 3 9,10,11 -20 -90 mA current 1/ VCC= 6.0 V, VO= 0.5 V 01-08, 12 Off-state output current IOZLVCC= 5.5 V, VO= 0.4 V 1, 2, 3 11 -50 A Off-state output current IOZHVCC= 5.5 V, VO=
42、2.4 V 1, 2, 3 11 50 A Supply current ICCVCC= 5.5 V Inputs low, outputs open 1, 2, 3 01,05, 12 160 02,03, 06,07 180 mA 04, 08 200 9,10,11 120 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING
43、SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min
44、Max Input capacitance CINVIN= 0 V, f = 1.0 MHz TA= +25C, see 4.3.1c 4 12 8 pF Input / output capacitance COUTVOUT= 0 V, f = 1.0 MHz TA= +25C, see 4.3.1c 4 12 12 pF Functional tests See 4.3.1d 7, 8A, 8B 12 Shift out high to output ready low tORLSee figure 3 9,10,11 01-08, 12 65 ns 9,10,11 55 Shift ou
45、t low to output ready high tORH9,10,11 01,02, 05,06 70 ns 03,04, 07,08, 12 65 9,10,11 55 Shift out rate 2/ fOUT9,10,11 01,02, 05,06 7 MHz 03,04, 07,08 10 9,10,11 12 12 16 Output data hold tODH9,10,11 All 10 ns Output data shift tODS9,10,11 01,02, 05,06 65 ns 03,04, 07,08, 12 60 9,10,11 50 Output rea
46、dy high to data valid tORD9,10,11 All 0 ns Shift out high time 2/ tSOH9,10,11 01,02, 05,06 45 ns 03,04, 07,08, 12 35 9,10,11 28 Shift out low time 2/ tSOL9,10,11 01,02, 05,06 45 ns 03,04, 07,08, 12 35 9,10,11 18 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networkin
47、g permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87791 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Shift in rate 2/ fINSee figure 4 9,10,11 01,02, 05,06 7 MHz 03,04, 07,08 10 9,10,11 12 12 16 Shift in high to input ready low tIRL9,10,11 01,02, 05,06 60 ns 03,04, 07-12 50 Shift in low to input
