1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R050-92. 91-11-19 Monica L. Poelking B Add case outline 2. Redraw the waveforms and add test circuit and notes to figure 4, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements
2、. Editorial changes throughout. - LTG 05-11-28 Thomas M. Hess C Update test condition of IOHand IOLvalues for High and Low output voltage to table I. Update boilerplate paragraphs to current MIL-PRF-38535 requirements. - MAA 11-07-26 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATU
3、S REV C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APP
4、ROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, OCTAL D-TYPE FLIP-FLOP WITH ENABLE, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-05-15 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 14933 5962-87807 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E436-11 Pr
5、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirement
6、s for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87807 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see
7、 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC377 Octal D-type flip-flop with enable 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive
8、designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (V
9、IN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ . 500 mW Lead temperature (
10、soldering, 10 seconds) 260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) 175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) 0.0 V dc to VCCCase ope
11、rating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot
12、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time, enable o
13、r input D to clock (ts): TC= +25C: VCC= 2.0 V . 100 ns VCC= 4.5 V . 20 ns VCC= 6.0 V . 17 ns TC= -55C to +125C: VCC= 2.0 V . 150 ns VCC= 4.5 V . 30 ns VCC= 6.0 V . 25 ns Minimum clock pulse width (tw): TC= +25C: VCC= 2.0 V . 100 ns VCC= 4.5 V . 20 ns VCC= 6.0 V . 17 ns TC= -55C to +125C: VCC= 2.0 V
14、. 150 ns VCC= 4.5 V . 30 ns VCC= 6.0 V . 25 ns Minimum hold time, input D to clock (th1): TC= +25C: VCC= 2.0 V . 5 ns VCC= 4.5 V . 5 ns VCC= 6.0 V . 5 ns TC= -55C to +125C: VCC= 2.0 V . 5 ns VCC= 4.5 V . 5 ns VCC= 6.0 V . 5 ns Minimum hold time, enable to clock (th2): TC= +25C: VCC= 2.0 V . 5 ns VCC
15、= 4.5 V . 5 ns VCC= 6.0 V . 5 ns TC= -55C to +125C: VCC= 2.0 V . 5 ns VCC= 4.5 V . 5 ns VCC= 6.0 V . 5 ns Maximum clock frequency (fMAX): TC= +25C: VCC= 2.0 V . 5 MHz VCC= 4.5 V . 25 MHz VCC= 6.0 V . 29 MHz TC= -55C to +125C: VCC= 2.0 V . 3 MHz VCC= 4.5 V . 16 MHz VCC= 6.0 V . 19 MHz Provided by IHS
16、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handb
17、ooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits,
18、Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Stan
19、dard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text
20、of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in
21、 accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL
22、-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modificati
23、ons shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions.
24、 The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth t
25、able. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unles
26、s otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests f
27、or each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 3.5 Marking. Mar
28、king shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the op
29、tion of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance
30、with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Lan
31、d and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall
32、be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the a
33、cquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN
34、DARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min
35、Max High level output voltage VOHVIN= VIHminimum or VILmaximum IOH= -20 A VCC= 2.0 V 1, 2, 3 All 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHminimum or VILmaximum IOH= -4.0 mA VCC= 4.5 V 3.7 VIN= VIHminimum or VILmaximum IOH= -5.2 mA VCC= 6.0 V 5.2 Low level output voltage VOLVIN= VIHminimum or VILm
36、aximum IOL= + 20 A VCC= 2.0 V 1, 2, 3 All 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHminimum or VILmaximum IOL= +4.0 mA VCC= 4.5 V 0.4 VIN= VIHminimum or VILmaximum IOL= +5.2 mA VCC= 6.0 V 0.4 High level input voltage 2/ VIHVCC= 2.0 V 1, 2, 3 All 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input
37、 voltage 2/ VILVCC= 2.0 V 1, 2, 3 All 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent supply current ICCVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Input capacitance CINVCC= GND, TC= 25C See 4.3.1c 4 All 10.0 pF Functional tests Se
38、e 4.3.1d 7 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Elec
39、trical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Propagation delay time, clock to Qn 3/ tPHL, tPLHCL= 50 pF See figure 4 VCC= 2.0 V 9 All 205 ns 10, 11 310 VCC= 4.5 V 9 4110, 11 62 VCC= 6
40、.0 V 9 3510, 11 53 Transition time 4/ tTLH, tTHLCL= 50 pF See figure 4 VCC= 2.0 V 9 All 75 ns 10, 11 110 VCC= 4.5 V 9 1510, 11 22 VCC= 6.0 V 9 1310, 11 19 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when
41、 designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically
42、30 pF, determine the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ Tests are not required if applied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to
43、the specified limits. 4/ Transition times (tTLH, tTHL), if not tested, shall be guaranteed to the specified limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 4
44、3218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Device type All Case outlines R and 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ENABLE GnullQ1 D1 D2 Q2 Q3 D3 D4 Q4 GND CLOCK Q5 D5 D6 Q6 Q7 D7 D8 Q8 VCCFIGURE 1. Terminal connections. Operating mode In
45、puts Outputs Clock Enable Dn Qn Load “1” l h H Load “0” l l L Hold (do nothing) X h H X X No change No change H = High voltage level steady state h = High voltage level one setup time prior to the low-to-high clock transition L = Low voltage level steady state l = Low voltage level one setup time pr
46、ior to the low-to-high clock transition = Low-to-high clock transition X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-39
47、90 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87807 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC
48、FORM 2234 APR 97 NOTES: 1. CL= 50 pF minimum or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to VCC; PRR 1 MHz; ZO= 50; tr= 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.1 VCCto 0.9 VCCand from 0.9 VCCto 0.1 VCC, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switc
