1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Delete vendor CAGE 27014. Change vendor CAGE 18714 to 34371. Add vendor CAGE 01295. Change drawing CAGE code to 67268. Change to table II and figure 4. Editorial changes throughout. - mbk 90-09-14 Michael A. Frye B Redraw the switching waveforms
2、and add notes to figure 4, switching waveforms and test circuit. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak 06-03-13 Thomas M. Hess C Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-02-14 Thomas M.
3、 Hess CURRENT CAGE CODE 67268 REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAIL
4、ABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Ricciuti APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL INVERTING BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-04-14 REVISION LE
5、VEL C SIZE A CAGE CODE 14933 5962-87809 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E181-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C
6、SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-
7、87809 01 R A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC640 Octal inverting bus transceiver with three-state outputs 1.2.
8、2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38
9、535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) 20 mA DC output diode current (per pin) (IOU
10、T) 35 mA DC VCCor GND current (per pin) 70 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operat
11、ing conditions. Supply voltage range (VCC) . +2.0 V dc to +6.0 V dc Case operating temperature range (TC) -55C to +125C Input voltage range (VIN) . 0.0 V dc to VCC Output voltage range (VOUT) 0.0 V dc to VCCInput rise or fall time (tr, tf): VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0
12、 V . 0 to 400 ns _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters s
13、pecified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 8 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
14、87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unles
15、s otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. M
16、IL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the
17、 Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicita
18、tion or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North
19、10thStreet, Suite 240-S Arlington, VA 22201-2107). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a s
20、pecific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Lis
21、ting (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML fl
22、ow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MI
23、L-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with
24、 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switc
25、hing waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234
26、 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be th
27、e subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packa
28、ges where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-385
29、35, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed
30、as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements
31、 herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change
32、that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option o
33、f the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteris
34、tics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHminimum or VILmaximum IOH= -20 A 2.0 V 1, 2, 3 1.9 V 4.5 V 4.4 6.0 V 5.9 VIN= VIHminimum or VILmaximum IOH= -6.0 mA 4.5 V 3.7 VIN= VIHminimum or
35、 VILmaximum IOH= -7.8 mA 6.0 V 5.2 Low level output voltage VOLVIN= VIHminimum or VILmaximum IOL= +20 A 2.0 V 1, 2, 3 0.1 V 4.5 V 0.1 6.0 V 0.1 VIN= VIHminimum or VILmaximum IOL= +6.0 mA 4.5 V 0.4 VIN= VIHminimum or VILmaximum IOL= +7.8 mA 6.0 V 0.4 High level input voltage VIH2/ 2.0 V 1, 2, 3 1.5 V
36、 4.5 V 3.15 6.0 V 4.2 Low level input voltage VIL2/ 2.0 V 1, 2, 3 0.3 V 4.5 V 0.9 6.0 V 1.2 Input capacitance CINTC+25C, see 4.3.1c GND 4 10 pF Input/output capacitance CI/OTC+25C, see 4.3.1c 3/ 6.0 V 4 20 pF Quiescent supply current ICCVIN= VCCor GND 6.0 V 1, 2, 3 160 A Input leakage current IINVIN
37、= VCCor GND 6.0 V 1, 2, 3 1 A Three-state output current IOZVOUT= VCCor GND G = VIH6.0 V 1, 2, 3 10 A Functional tests See 4.3.1d 7, 8 Propagation delay time, An to Bn or Bn to An tPHL, tPLH4/ CL= 50 pF10% See figure 4 2.0 V 9 105 ns 10, 11 160 4.5 V 9 21 ns 10, 11 32 6.0 V 9 18 ns 10, 11 27 See foo
38、tnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance cha
39、racteristics Continued. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max Propagation delay time, output enable, G to An or Bn tPZH, tPZL4/CL= 50 pF10% RL= 1 k See figure 4 2.0 V 9 230 ns 10, 11 340 4.5 V 9 46 ns 10, 11 68 6.0 V 9 41 ns
40、10, 11 58 Propagation delay time, output disable, G to An or Bn tPHZ, tPLZ4/ CL= 50 pF10% RL= 1 k See figure 4 2.0 V 9 172 ns 10, 11 255 4.5 V 9 43 ns 10, 11 56 6.0 V 9 41 ns 10, 11 54 Transition time tTLH, tTHL 5/ CL= 50 pF10% See figure 4 2.0 V 9 60 ns 10, 11 90 4.5 V 9 12 ns 10, 11 18 6.0 V 9 10
41、ns 10, 11 15 1/ For power supply of 5 V 10 percent, the worst case output voltages (VOHand VOL) occur for high-speed CMOS at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is
42、 3.85 V). The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage, so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 100 pF, determines the no load dynamic power consumption, PD= CPDVCC2 f + ICCVCC, and the no load dynamic current con
43、sumption, IS= CPDVCCf + ICC. 2/ VIHand VILtests are not required if applied as a forcing function for VOHor VOLtests. 3/ Set the output enable control pin to VCCor GND, as applicable, to disable the outputs of the device. 4/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested,
44、 to the specified limits in table I. 5/ Transition times (tTLHand tTHL), if not tested, shall be guaranteed to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND A
45、ND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines R and 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND B8 B7 B6 B5 B4 B3 B2 B1 G VCCFIGURE 1. Terminal connections. Co
46、ntrol inputs Operation G DIR L L B data to A bus L H A data to B bus H X Isolation L = Low voltage level H = High voltage level X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A
47、 5962-87809 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87809 DLA LAND AND MARITIME
48、COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. CL= 50 pF or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to VCC; PRR 1 MHz; ZO= 50; tr= 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.1VCCto 0.9VCCand from 0.9VCCto 0.1VCC, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo
