1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Removed logic diagram. Editorial changes throughout. - gap 01-11-01 Raymond Monnin B Update boilerplate for 5 year review. lhl 11-05-20 Charles F. Saffle THE ORIGINAL FRONT PAGE HAS BEEN REPLACED. REV SHEET
2、 REV SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing THIS DRAWING IS AVAILABLE FOR US
3、E BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, BIPOLAR, FIELD PROGRAMMABLE SEQUENCER (FPLS), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-01-22 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-88507 SHEET 1 OF 14 DSCC FOR
4、M 2233 APR 97 5962-E329-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing
5、 describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88507 01 L A Drawing number Device type (see 1.2.1) Case outli
6、ne (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 PLS179 (20 x 45 x 12) field programmable logic sequencer 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-18
7、35 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . 7.0 V dc Input voltage 10.0 V dc Output voltage .
8、5.5 V dc Input current (minimum) -30 mA Input current (maximum) . 30 mA Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1/ . 1.2 W Thermal resistance, junction-to-case (JC): Case L See MIL-STD-1835 Junction temperature (TJ) +200C Output sink current 100 mA 1.4 Recommended op
9、erating conditions. Supply voltage (VCC) 4.5 V dc to 5.5 V dc Minimum high level input voltage (VIH) 2.2 V dc Maximum low level input voltage (VIL) . 0.8 V dc Case operating temperature range (TC) -55C to +125C _ 1/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot
10、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbook
11、s. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Man
12、ufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standar
13、d Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of t
14、his drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in acc
15、ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF
16、-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications
17、shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used 3.2 Design, construction, and physical dimensions. The
18、design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The t
19、ruth table shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduc
20、tion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified
21、 in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see
22、6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in com
23、pliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer
24、in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A
25、 and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be requ
26、ired for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available ons
27、hore at the option of the reviewer. 3.10 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.10.1
28、Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.3.1c and table II. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.10.2 Manufacturer-programmed device delivered t
29、o the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with
30、MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A,
31、 B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance
32、 with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNo
33、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -
34、55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Low level input voltage VILVCC= 4.5 V 1, 2, 3 0.8 V High level input voltage VIHVCC= 5.5 V 1, 2, 3 2.2 V Input clamp voltage 2/ VICVCC= 4.5 V, II= -18 mA 1, 2, 3 -1.2 V Low level input current IILVCC= 5.5 V
35、, VI= 0.45 V 1, 2, 3 -100 A Low level input current IILVCC = 5.5 V, VI = 0.45 V 1, 2, 3 -250 A (CLK input) High level input current IIHVCC= 5.5 V, VI= 5.5 V 1, 2, 3 40 A Low level output voltage VOLVCC= 4.5 V, VIL= 0.8 V, 1, 2, 3 0.5 V VIH= 2 V, IOL= 10 mA High level output voltage VOHVCC= 4.5 V, VI
36、L= 0.8 V, 1, 2, 3 2.4 V VIH= 2 V, IOH= -2 mA Output short-circuit IOSVCC= 4.5 V, VO= 0 V 1, 2, 3 -15 -85 mA current 2/ 3/ DC supply current 4/ ICCVCC= 5.5 V 1, 2, 3 210 mA Three-state output current IOZVCC = 5.5 V VOUT = 5.5 V 1, 2, 3 80 A 5/ 6/ VOUT = 0.45 V -140 A Functional tests See 4.3.1d 7, 8
37、Propagation delay: tCKOVCC= 5.0 V 10% 9, 10, 11 25 ns Clock R1= 470, R2= 1 k, CL= 50 pF Output enable tOE1See figures 3 and 4 9, 10, 11 35 ns To prevent spurious clocking, Output disable 7/ t0D1clock rise time (10%-90%) 10 ns 9, 10, 11 35 ns See footnotes at end of table. Provided by IHSNot for Resa
38、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/
39、 -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Output tPDVCC= 5.0 V 10% 9, 10, 11 40 ns R1= 470, R2= 1 k, CL= 50 pF Output enable tOE2See figures 3 and 4 9, 10, 11 40 ns To prevent spurious clocking, Output disable 7/ tOD2clock rise time (10%-90%) 10
40、ns 9, 10, 11 40 ns Preset/reset tPRO9, 10, 11 50 ns Power-on preset tPPR9, 10, 11 20 ns Pulse width: Clock high 7/ 8/ tCKH9, 10, 11 25 ns Clock low 8/ tCKL9, 10, 11 25 ns Period 8/ tCKP9, 10, 11 65 ns Preset/reset pulse 8/ tPRH9, 10, 11 45 ns Setup time: Input 8/ tIS19, 10, 11 40 ns Input (through F
41、N) 8/ tIS29, 10, 11 25 ns Input (through complement tIS39, 10, 11 65 ns array) 8/ 9/ Hold time: Input 8/ tIH19, 10, 11 0 ns Input (through FN) 8/ tIH29, 10, 11 15 ns 1/ All voltage values are with respect to ground. 2/ Test one at a time. 3/ Duration of short circuit should not exceed 1 second. 4/ I
42、CCis measured with the OE input grounded, all other inputs at 4.5 V, and the outputs open. 5/ Measured with VIHapplied to OE . 6/ Leakage values are a combination of input and output leakage. 7/ Measured at VT= VOL+0.5 V. 8/ Limits are guaranteed with 12 product terms maximum connected to each sum t
43、erm line. 9/ When using the complement array tVKP= 75 ns (minimum). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 223
44、4 APR 97 Case outline L Terminal Terminal number symbol 1 CLK 2 I03 I14 I25 I36 I47 I58 I69 I710 B011 B112 GND 13 OE 14 B215 F016 F117 F218 F319 F420 F521 F622 F723 B324 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
45、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 OE L CK P R J K Q F H H/Hi-Z L X X L X X X L H L X X H L X X H L L X X L H X X L H L L L L L L Q Q L L L L L H L H L L L L H L H L L L L L H H Q Q H H L L
46、 L H L H* H H L L H L H L* +10 V X X X L H L H* X X X H L H L* NOTES: 1. Positive logic: J/K = T0+ T1+ T2+. +T32Tn = C (I0 I1 I2) (Q0 Q1) (B0 B1) 2. denotes transition from low to high level. 3. X = Dont care. 4. * = Forced at Fn pin for loading J/K flip-flop in I/O mode. L must be enabled, and othe
47、r active tn disabled via steering input(s) I, B, or Q. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. * = Forced at Fn pin to load J/K flip-flop independent of program code (diagnostic mode). FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or
48、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88507 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Test load circuit. Input pulse characteristics VMRep. rate Pulse width tTLHtTHL1.5 V 1 MHz 500 ns 5 ns 5 ns FIGURE 4. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or n
