1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R191-92 92-04-17 Michael A. Frye B Update boilerplate for 5 year review. lhl 11-06-20 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV B SHEET 15 REV STATUS REV B B B B
2、 B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin THIS DRAWING IS AVAILAALE FOR USE AY ALL DEPARTMENTS APPROVED BY Michael
3、A. Frye MICROCIRCUITS, MEMORY, DIGITAL, CMOS, UV ERASABLE, PROGRAMMABLE LOGIC DEVICE AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 12 JULY 1989 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-88549 B SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E350-11 Provided by IHSNot for Resale
4、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant
5、, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part number. The complete part number shall be as shown in the following example: 5962-88549 01 X A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). Th
6、e device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 EP1800 1800 gate CMOS UV EPLD 90 ns 02 EP1800 1800 gate CMOS UV EPLD 75 ns 1.2.2 Case outlines. The case outlines shall be as designated in MIL-STD-1835 and as follows: Outline lette
7、r Descriptive designator Terminals Package style X CMGA3-P68 68 pin grid array package Y CMGA15-P68 68 pin grid array package Z See figure 1 68 flat package U GQCC1-J68 68 J-lead chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rating
8、s. Supply voltage range (VCC). -0.5 V dc to +7.0 V dc Programming supply voltage range (VPP). -0.5 V dc to +13.5 V dc DC input voltage range (VIN) 1/. -0.5 V dc to VCC+0.5 V dc DC output voltage range (VO) -0.5 V dc to VCC+0.5 V dc DC output current (IO) . 25 mA dc Storage temperature range -65C to
9、+150C Maximum power dissipation (PD) 1.5 W Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ). +200C DC supply current (ICCor ISS). 300 mA 1.4 Recommended operating conditions. Supply voltage range (VCC). 4.5 V dc to 5.
10、5 V dc High level input voltage range (VIH) 2.0 V dc to VCC+0.3 V dc Low level input voltage range (VIL). -0.3 V dc to +0.8 V dc Input rise time (tr) 500 ns maximum Input fall time (tf) 500 ns maximum Supply voltage rise time (trvcc). 10 ns maximum Clock rise time (trclk) 100 ns maximum Clock fall t
11、ime (tfclk) 100 ns maximum Case operating temperature range (TC) -55C to +125C _ 1/ Minimum dc input voltage is -0.5 V dc. During transitions, the inputs may undershoot to -2.0 V dc or overshoot to 7.0 V dc for periods of less than 20 ns. Provided by IHSNot for ResaleNo reproduction or networking pe
12、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards,
13、and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPA
14、RTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these d
15、ocuments are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herei
16、n, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for
17、 non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in
18、accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of
19、 the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimens
20、ions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. 3.2.3.1 Unprogrammed devices. T
21、he truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 3. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, C or D (see 4.3), the devices shall be programmed by the manufacturer prior to
22、test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical
23、 performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Additionally the low power standby power mode is disabled. 3.4 Electrical test requirements. The ele
24、ctrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88549 DLA LAND AND MARITI
25、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the
26、 entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.6 Processing EPLDS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of
27、 EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.6.2 Programmability of EPLDS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.6.3 Verification o
28、f erasure of programmability of EPLDS. When specified, devices shall be verified as either programmed to the specific pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify
29、 to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of
30、 compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in
31、MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.10 Verification and review. DLA Land and Maritime, DLA La
32、nd and Maritimes agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection p
33、rocedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015
34、 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipatio
35、n, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the
36、manufacturer. c. All devices selected for testing shall be programmed as specified to the footnotes of table I, after completion of all testing, the devices shall be erased and verified to be erased. d. A data retention stress test shall be included as part of the screening procedure (may be perform
37、ed prior to the internal visual inspection of method 5004 of MIL-STD-883 at the discretion of the manufacturer) and shall consist of the following steps: Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88549
38、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 Margin test method: A 1. Each device shall be verified to be erased by a full function test. Each device shall then have greater than 99 percent of all bit locations programmed and verified. 2. Each device
39、 shall then be subjected to an unbiased retention bake at 140C for 72 hours minimum (or equivalent time and temperature implied by an activation energy of 0.4 eV). 3. After the retention bake, each device shall again be verified. Each device shall then be electrically tested with guardbanding. A mar
40、gin voltage of VCC= 5.9 V dc (minimum) shall be used, and each programmed bit shall be verified to maintain the proper logic state. All remaining user bits not programmed before retention bake shall be programmed and verified, except the security bit. 4. Any device containing a bit which does not ve
41、rify as programmed, or erased, as applicable, or which does not maintain the proper logic state during margin testing, shall be rejected and shall not be delivered to this drawing. Margin test method: B 1. Each device shall be verified to be erased by a full functional test. Each device shall then h
42、ave all user bit locations programmed and verified. 2. Each device shall then be subjected to an unbiased retention bake at 140C for 72 hours minimum (or equivalent time and temperature implied by an activation energy of 0.4 eV). 3. After the retention bake, each device shall again be verified. Each
43、 device shall then be electrically tested with guardbanding. A margin voltage of VCC= 5.9 V dc (minimum) shall be used, and each programmed bit shall be verified to maintain the proper logic state. 4. Any device containing a bit which does not verify as programmed, or erased, as applicable, or which
44、 does not maintain the proper logic state during margin testing, shall be rejected and shall not be delivered to this drawing. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The fo
45、llowing additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN, COUT, CCLKand CVPPmeasurements) shall be measured only for the initial qualification
46、 and after process or design changes which may affect capacitance. Sample size is 15 devices with no failures, and all input and output terminals tested. d. As a minimum, subgroups 7 and 8 shall consist of verifying the EPLD pattern as specified to the footnotes of table I. e. All devices selected f
47、or testing shall be programmed as specified to the footnotes of table I, after completion of all testing, the devices shall be erased and verified to be erased. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C 4.
