1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add “Changes in accordance with NOR 5962-R295-92“. 92-09-02 M. L. Poelking B Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 01-02-05 Raymond Monnin C Update drawing to current requirements. Editori
2、al changes throughout. - gap 08-07-23 Robert M. Heber The original first sheet of this drawing has been replaced. REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Christopher A. Rauch DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICR
3、OCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED LOW POWER SCHOTTKY TTL, INVERTING, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING A
4、PPROVAL DATE 88-04-27 OCTAL BUFFER AND LINE DRIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-88591 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E161-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
5、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with
6、MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88591 01 S X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as fol
7、lows: Device type Generic number Circuit function 01 54ALS240 Inverting octal buffer and line driver with three-state output 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style S GDFP2-F20 or CDFP3
8、-F20 20 Flat package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage . -0.5 V dc to +7.0 V dc Input voltage (VIN) . -1.2 V dc at -18mA to +7.0 V dc Voltage applied to a disable 3-state output . 5.5 V dc Storage temperat
9、ure range . -65C to +150C Maximum power dissipation (PD) . 137.5 mW 2/ Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc M
10、inimum high-level input voltage (VIH) +2.0 V dc Maximum low level input voltage (VIL): TC= +125C . 0.7 V dc TC= -55C . 0.8 V dc TC= +25C . 0.8 V dc Case operating temperature range (TC) -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended o
11、peration at the maximum levels may degrade performance and affect reliability. 2/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short circuit test; e.g., I0S. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S
12、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of
13、this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS M
14、IL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online
15、 at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing ta
16、kes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices
17、 and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufactur
18、ers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modificatio
19、ns shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
20、MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. Th
21、e logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as
22、specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo repro
23、duction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part sh
24、all be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/comp
25、liance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Ce
26、rtificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the
27、 manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification o
28、f change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shal
29、l be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on
30、 all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made availab
31、le to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters sha
32、ll be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFE
33、NSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C Group A subgroups Limits Unit unless otherwise specified Min Max High level output voltage VIL= 0.8 V 1, 3 VOH1V
34、IH= +2.0 V, VCC= +4.5 V, IOH= -12 mA 2/ VIL= 0.7 V 2 2.0 V VIL= 0.8 V 1, 3 VOH2VIH= +2.0 V, VCC= +4.5 V, IOH= -3 mA 2/ VIL= 0.7 V 2 2.4 V VIL= 0.8 V 1, 3 VOH3VIH= +2.0 V, VCC= +4.5 V, IOH= -0.4 mA 2/ VIL= 0.7 V 2 2.5 V VIL= 0.8 V 1, 3 Low level output voltage VOLIOL= +12 mA VCC= +4.5 V, VIH= +2.0 V
35、2/ VIL= 0.7 V 2 0.4 V Input clamp voltage VICIIN= -18 mA, VCC= +4.5 V 1, 2, 3 -1.2 V Off-state output current IOZHVCC= +5.5 V, VIH= +2.0 V, VOUT= +2.7 V 1, 2, 3 20 A IOZLVCC= +5.5 V, VIH= +2.0 V, VOUT= +0.4 V 1, 2, 3 -20 High level input current IIH1VCC= +5.5 V, VIN= +2.7 V, All other inputs = 0.0 V
36、 1, 2, 3 20 A IIH2VCC= +5.5 V, VIN= +7.0 V, All other inputs = 0.0 V 1, 2, 3 0.1 mA Low level input current IILVCC= +5.5 V, VIN= 0.4 V, All other inputs = 4.5 V 1, 2, 3 -0.1 mA Output current IOVCC= +5.5 V, VOUT= 2.25 V 3/ 1, 2, 3 -20 -112 mA Supply current ICCHVCC= +5.5 V 1, 2, 3 11 mA ICCL1, 2, 3
37、23 mA Supply current disabled ICCZ1, 2, 3 25 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C S
38、HEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC+125C 1/ Group A subgroups Limits Unit unless otherwise specified Min Max Functional tests See 4.3.1c 4/ 7, 8 tPLH 9, 10, 11 2 12 ns Propagation delay time, A to Y tPHL 9, 10, 11 2
39、 9 ns tPZL 9, 10, 11 5 18 ns Output enable time, Gto Y tPZH 9, 10, 11 4 15 ns tPLZ 9, 10, 11 3 15 ns Output disable time, Gto Y tPHZ VCC= 4.5 V to 5.5 V, CL= 50 pF, 5/ RL1= 500 5% , RL2= 500 5% See figure 4 9, 10, 11 1 10 ns 1/ Unused inputs that do not directly control the pin under test must be 2.
40、5 V or 0.4 V. No unused inputs shall exceed 5.5 V or go less than 0.0 V. No input shall be floated. 2/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum produces the proper output state, the test must be performed with each input being selected as the VILmaximu
41、m or VIHminimum input. 3/ The output conditions have been chosen to produce a current that closely approximates on half of the true short circuit output current, IOS. Not more than one output shall be tested at one time, and the duration of the test condition shall not exceed one second. 4/ Function
42、 tests shall be conducted at input test conditions of GND VIL VOLand VOH VIH VCC. 5/ Propagation delay limits are base on single output switching. Unused inputs = 3.5 V or 0.3 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT D
43、RAWING SIZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outline S Terminal number Terminal symbol 1 G 2 1A1 3 2Y4 4 1A2 5 2Y3 6 1A3 7 2Y2 8 1A4 9 2Y1 10 GND 11 2A1 12 1Y4 13 2A2 14 1Y3 15 2A3 16 1Y2 17 2A4 1
44、8 1Y1 19 2G 20 VCCFIGURE 1. Terminal connections. Inputs Output G A Y H X Z L L L L H H H = High level L Low level X Irrelevant Z = High impedance FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI
45、ZE A 5962-88591 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE S
46、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88591 DEFENSE SUP
47、PLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses have the following characteristics: PRR 10 MHz, duty cycle = 50%, tr= 3 ns 1 ns, tf= 3 ns 1 ns. 3. The outputs are measured one at a time
48、with one input transition per measurement. 4. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 5. When measuring propagation delay times of three-state outputs, switch S1 is open. FIGURE 4. Switching waveforms and test circuit - Continued. Provided by IHSNot for R
